WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 144

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8310
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23.2.2
The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26.
The secondary interrupt bit is defined in Table 88.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a TEMP_INT interrupt. The secondary interrupt bit in R16401 (4011h)
is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.
R16401
(4011h)
Interrupt Status
1
R16410
(4019h)
Interrupt Status
1 Mask
Table 88 Thermal Interrupts
23.2.3
The primary GP_INT interrupt comprises twelve secondary interrupts as described in Section 21.4.
The secondary interrupt bits are defined in Table 89.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a GP_INT interrupt. The secondary interrupt bits in R16405
(4015h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
R16405
(4015h)
Interrupt Status
5
R16413
(401Dh)
Interrupt Status
5 Mask
Note: n is a number between 1 and 12 that identifies the individual GPIO.
Table 89 GPIO Interrupts
23.2.4
The primary ON_PIN_INT interrupt comprises a single secondary interrupt as described in
Section 11.6. The secondary interrupt bit is defined in Table 90.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger an ON_PIN_INT interrupt. The secondary interrupt bit in R16401
(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by
default.
ADDRESS
ADDRESS
THERMAL INTERRUPTS
GPIO INTERRUPTS
ON PIN INTERRUPTS
11:0
11:0
BIT
BIT
1
1
TEMP_THW_CINT
IM_TEMP_THW_CINT
GPn_EINT
IM_GPn_EINT
LABEL
LABEL
Thermal Warning interrupt
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
GPIO interrupt.
(Trigger is controlled by GPn_INT_MODE)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
PP, December 2009, Rev 3.0
DESCRIPTION
DESCRIPTION
Pre-Production
144