ISP1504A1ETTM ST-Ericsson Inc, ISP1504A1ETTM Datasheet - Page 25

• Manufacturer Part Number: ISP1504A1ETTM
• Description: IC USB TXRX HS 36-TFBGA
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1504A1ETTM

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1504A1ET-T; ISP1504A1ET-T

NXP Semiconductors
ISP1504A1_ISP1504C1_1
Product data sheet
Fig 7. Interface behavior with respect to RESET_N
DATA[7:0]
RESET_N
CLOCK
NXT
STP
DIR
9.3.1 Interface protection
9.3.2 Interface behavior with respect to RESET_N
9.3.3 Interface behavior with respect to CS_N/PWRDN
Hi-Z (input)
Hi-Z (input)
By default, the ISP1504x1 enables a weak pull-up resistor on STP. If the STP pin is
unexpectedly HIGH at any time, the ISP1504x1 will protect the ULPI interface by enabling
weak pull-down resistors on DATA[7:0].
The interface protect feature prevents unwanted activity of the ISP1504x1 whenever the
ULPI interface is not correctly driven by the link. For example, when the link powers up
more slowly than the ISP1504x1.
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
If the interface protect feature is not needed, it must be disabled to reduce power
consumption.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1504x1 will assert DIR. All logic in the ISP1504x1 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is de-asserted (HIGH), the
DIR output will de-assert (LOW) four or five clock cycles later.
interface behavior when RESET_N is asserted (LOW), and when RESET_N is
subsequently de-asserted (HIGH). The behavior of
CS_N/PWRDN is asserted (LOW). If RESET_N is not used, it must be tied to V
The use of the CS_N/PWRDN pin is optional. When de-asserted (HIGH), the
CS_N/PWRDN pin will 3-state ULPI pins and power down internal circuitry. If
CS_N/PWRDN is not used, it must be tied to LOW.
behavior when CS_N/PWRDN is asserted (LOW) and when CS_N/PWRDN is
subsequently de-asserted (HIGH). The behavior of
de-asserted (HIGH).
Hi-Z (link must drive)
Hi-Z (link must drive)
Rev. 01 — 6 August 2007
ISP1504A1; ISP1504C1
Hi-Z (input)
Hi-Z (input)
Figure 7
Figure 8
Figure 8
ULPI HS USB OTG transceiver
applies only when
shows the ULPI interface
assumes that RESET_N is
Figure 7
© NXP B.V. 2007. All rights reserved.
shows the ULPI
004aaa720
CC(I/O)
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