ISP1504A1ETTM ST-Ericsson Inc, ISP1504A1ETTM Datasheet
ISP1504A1ETTM
Specifications of ISP1504A1ETTM
ISP1504A1ET-T
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ISP1504A1ETTM Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1504A1; ISP1504C1 ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 6 August 2007 1. General description The ISP1504A1; ISP1504C1 (ISP1504x1 Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification ...
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NXP Semiconductors N Supports external charge pump Complete control over bus resistors N Data line and V N Integrated V N Integrated cable (ID) detector I Highly optimized ULPI-compliant interface N 60 MHz, 8-bit interface ...
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NXP Semiconductors I Mobile phone I MP3 player I PDA I Printer I Scanner I Set-Top Box (STB) I Video camera 4. Ordering information Table 1. Ordering information Part Type number Marking Crystal or clock frequency [1] ISP1504A1ET 504M 19.2 ...
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NXP Semiconductors 5. Block diagram A4 CLOCK B1, A1, A2, A3, A5, A6, 8 DATA B6, C6 [7:0] ULPI interface E5 DIR D6 STP D5 NXT C3 CS_N/PWRDN C4 RESET_N global clocks F5 XTAL1 F6 XTAL2 B2, B3, B5 interface ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration TFBGA36; top view 6.2 Pin description Table 2. Pin description [1][2] Symbol Pin Type DATA1 A1 I/O DATA2 A2 I/O DATA3 A3 I/O CLOCK A4 O DATA4 A5 I/O ...
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NXP Semiconductors Table 2. Pin description …continued [1][2] Symbol Pin Type CS_N PWRDN RESET_N C4 I DATA7 PSW_N D4 OD NXT D5 O STP D6 I FAULT E2 I REG3V3 ...
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NXP Semiconductors 7. Functional description 7.1 ULPI interface controller The ISP1504x1 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to the USB link. The ULPI interface ...
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NXP Semiconductors • Differential and single-ended receivers to receive data at high-speed, full-speed and low-speed • Squelch circuit to detect high-speed bus activity • High-speed disconnect detector • 45 • 1.5 k pull-up resistor on DP • pull-down ...
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NXP Semiconductors • The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which device is initially configured as the host and which as the peripheral. • V BUS detection, SRP and HNP. • ...
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NXP Semiconductors 7.7 Band gap reference voltage The band gap circuit provides a stable internal voltage reference to bias analog circuitry. The band gap requires an accurate external reference resistor. Connect resistor between the RREF pin and ...
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NXP Semiconductors 7.9.4 DP and DM DP (data plus) and DM (data minus) are USB differential data pins. These must be connected to the D+ and D pins of the USB receptacle. 7.9.5 FAULT If an external V circuit can ...
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NXP Semiconductors Table 3. Application OTG Standard host Standard peripheral Fig 3. Application circuit components 7.9.10 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1504x1 internal digital and analog circuits, and must not be used ...
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NXP Semiconductors 7.9.13 DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1504x1 holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1504x1 listens for data ...
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NXP Semiconductors 8. Modes of operation 8.1 ULPI modes The ISP1504x1 ULPI bus can be programmed to operate in five modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one ...
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NXP Semiconductors Table 4. Signal name DIR STP NXT 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1504x1 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that ...
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NXP Semiconductors Table 5. Signal mapping during low-power mode Signal Maps to LINESTATE0 DATA0 LINESTATE1 DATA1 Reserved DATA2 INT DATA3 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed ...
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NXP Semiconductors Table 7. Signal mapping for 3-pin serial mode Signal Maps to TX_ENABLE DATA0 DAT DATA1 SE0 DATA2 INT DATA3 Reserved DATA[7:4] 8.1.5 Power-down mode In this mode, the PHY will 3-state the DATA[7:0], CLOCK, NXT and DIR pins. ...
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NXP Semiconductors CS_N/PWRDN CLOCK DATA[7:0] DIR NXT STP Fig 4. Entering and exiting 3-state in normal mode 8.2 USB state transitions A Hi-Speed USB host or an OTG device handles more than one electrical state as defined in Universal Serial ...
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NXP Semiconductors Table 8. Operating states and corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] General settings 3-state drivers XXb Power < 01b BUS V B_SESS_END Host settings Host chirp 00b Host high-speed 00b Host ...
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NXP Semiconductors Table 8. Operating states and corresponding resistor settings Signaling mode Register settings XCVR SELECT [1:0] OTG device 01b peripheral high-speed and full-speed suspend OTG device 01b peripheral high-speed and full-speed resume OTG device 00b peripheral Test J or ...
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NXP Semiconductors 9. Protocol description This following subsections describe the protocol for using the ISP1504x1. 9.1 ULPI references The ISP1504x1 provides a 12-pin ULPI interface to communicate with the link highly recommended that you read UTMI+ Low Pin ...
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NXP Semiconductors The recommended power-up sequence for the link is: 1. The CS_N/PWRDN pin transitions from HIGH to LOW. 2. The link waits for 1 ms, ignoring all the ULPI pin status. 3. The link may start to detect DIR ...
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NXP Semiconductors CC(I/O) CS_N/ PWRDN REG1V8 t PWRUP internal REG1V8 detector internal POR XTAL1 CLOCK DATA[7:0] DIR STP NXT applied to the ISP1504x1 turned ...
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NXP Semiconductors 9.3.1 Interface protection By default, the ISP1504x1 enables a weak pull-up resistor on STP. If the STP pin is unexpectedly HIGH at any time, the ISP1504x1 will protect the ULPI interface by enabling weak pull-down resistors on DATA[7:0]. ...
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NXP Semiconductors CLOCK CS_N/PWRDN DATA[7:0] Hi-Z (input) DIR Hi-Z (input) STP NXT Fig 8. Interface behavior with respect to CS_N/PWRDN 9.4 V power and overcurrent detection BUS 9.4.1 Driving The ISP1504x1 supports external 5 V supplies. ...
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NXP Semiconductors 9.5.1 TXCMD By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1504x1 by sending a byte ...
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NXP Semiconductors Table 11. RXCMD byte format DATA Name Description and value LINESTATE LINESTATE signals: For a definition of LINESTATE, see DATA0 — LINESTATE[0] DATA1 — LINESTATE[ state Encoded V BUS 5 to ...
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NXP Semiconductors Table 13. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1. Mode Low-speed XCVRSELECT[1:0] 10 TERMSELECT 1 OPMODE[1:0] X LINESTATE[1:0] 00 SE0 01 LS-K 10 LS-J 11 SE1 [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates ...
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NXP Semiconductors USE_EXT_VBUS_IND, IND_PASSTHRU Fig 10. RXCMD A_VBUS_VLD indicator source 9.5.2.3 Using and selecting the V The V BUS link whenever there is a change in the V must first enable corresponding interrupts in the USB Interrupt Enable Rising Edge ...
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NXP Semiconductors OTG devices: provide a minimum there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD comparator is sufficient. If the OTG A-device provides more than 100 overcurrent ...
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NXP Semiconductors 9.6 Register read and write operations Figure 11 addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1504x1 asserts DIR during the operation. When a ...
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NXP Semiconductors than 7 ms after reset time T up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 ...
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NXP Semiconductors USB reset T 0 TXCMD (REGW) SE0 DATA [ 7:0 ] DIR STP NXT 01 (FS) XCVR SELECT TERM SELECT 00 (normal) OP MODE J (01b) SE0 (00b) LINE STATE TXCMD SE0 (REGW) DATA [ 7:0 ] DIR ...
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NXP Semiconductors 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . link sends TXCMD CLOCK TXCMD DATA [ 7:0 ] ...
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NXP Semiconductors Table 18. Link decision times Packet sequence High-speed link delay Transmit-Transmit (host only) Receive-Transmit (host or peripheral) Receive-Receive 1 (peripheral only) Transmit-Receive 92 (host or peripheral DATA DM CLOCK D ...
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NXP Semiconductors DP or DATA EOP DM CLOCK DATA [7: DIR STP NXT RX end delay (three to eight clocks) Fig 15. High-speed receive-to-transmit packet timing 9.9 ...
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NXP Semiconductors CLOCK DATA[7: Fig 16. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed or low-speed host-initiated suspend and resume Figure 17 suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note ...
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NXP Semiconductors idle DATA [ 7:0 ] DIR STP NXT OPMODE 00b LINE J STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT OPMODE SUSPEND M LINE STATE DP DM Timing is not to scale. Fig 17. Full-speed ...
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NXP Semiconductors The sequence of events related to a host and a peripheral, both with ISP1504x1 follows. 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN ...
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NXP Semiconductors HS idle TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE CLOCK TXCMD (REGW) DATA [ 7:0 ] DIR STP NXT XCVR 00b SELECT TERM ...
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NXP Semiconductors 9.10.3 Remote wake-up The ISP1504x1 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers what speed it was originally operating. Depending on the original speed, the link follows one of the ...
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NXP Semiconductors LINESTATE DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE TXCMD LINESTATE REGW DATA [ 7:0 ] DIR STP NXT XCVR SELECT TERM SELECT OP MODE Timing is not to scale. Fig 19. Remote ...
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NXP Semiconductors PHY will not transmit any EOP. The ISP1504x1 will also detect if the PID byte is A5h, indicating an SOF packet and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the ...
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NXP Semiconductors 9.12.1 OTG comparators The ISP1504x1 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 requirements of V and V B_SESS_END V A_SESS_VLD are communicated to the link by RXCMDs as described in comparators ...
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NXP Semiconductors SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV Fig 21. Example of transmit followed by receive in 6-pin serial mode SYNC DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 ...
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NXP Semiconductors 9.14 Aborting transfers The ISP1504x1 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4 . 9.15 Avoiding contention on the ULPI data bus Because the ULPI ...
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NXP Semiconductors 10. Register map Table 19. Immediate register set overview Field name Vendor ID Low register Vendor ID High register Product ID Low register Product ID High register Function Control register Interface Control register OTG Control register USB Interrupt ...
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NXP Semiconductors 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 21 Table 21. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access VENDOR_ID_ R ...
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NXP Semiconductors Table 26. Function Control register (address R = 04h to 06h 04h 05h 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Sets the ...
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NXP Semiconductors Table 28. Interface Control register (address R = 07h to 09h 07h 08h 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1504x1 to protect ...
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NXP Semiconductors Table 30. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit description Bit Symbol Description 7 USE_EXT_VBUS Use External V _IND 0b — Use the internal OTG comparator. ...
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NXP Semiconductors Table 32. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description Bit Symbol Description reserved 4 ID_GND_R ID Ground Rise: ...
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NXP Semiconductors Table 35. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 Symbol reserved Reset X Access R Table 36. USB Interrupt Status register (address R = 13h) bit description Bit Symbol ...
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NXP Semiconductors 10.1.9 Debug register The bit allocation of the Debug register is given in current value of signals useful for debugging. Table 39. Debug register (address R = 15h) bit allocation Bit 7 Symbol Reset 0 Access R Table ...
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NXP Semiconductors Table 43. Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit description Bit Symbol Description reserved; the link must never write logic 1 to ...
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NXP Semiconductors 11. Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input/output supply voltage CC(I/O) V input voltage I V electrostatic discharge ESD voltage I ...
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NXP Semiconductors 13. Static characteristics Table 46. Static characteristics: supply pins CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 47. Static characteristics: digital pins CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, CS_N/PWRDN CC(I/O) Typical values are 3.6 V; ...
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NXP Semiconductors Table 50. Static characteristics: analog I/O pins CC(I/O) Typical values are 3 Symbol Parameter ...
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NXP Semiconductors Table 51. Static characteristics: analog pin CC(I/O) Typical values are 3 Symbol Parameter Comparators V ...
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NXP Semiconductors 14. Dynamic characteristics Table 54. Dynamic characteristics: reset and clock CC(I/O) Typical values are 3 Symbol ...
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NXP Semiconductors Table 55. Dynamic characteristics: digital I/O pins CC(I/O) Typical values are 3 Symbol Parameter V = ...
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NXP Semiconductors Table 57. Dynamic characteristics: analog I/O pins DP and CC(I/O) Typical values are 3 Symbol ...
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NXP Semiconductors Table 57. Dynamic characteristics: analog I/O pins DP and CC(I/O) Typical values are 3 Symbol ...
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NXP Semiconductors CONTROL IN DATA IN CONTROL OUT (DIR, NXT) DATA OUT Fig 27. ULPI timing interface Fig 28. Bus turnaround timing ISP1504A1_ISP1504C1_1 Product data sheet CLOCK t t su(STP) h(STP) (STP su(DATA) h(DATA) (8-BIT) (8-BIT) CLOCK DATA[7:0] ...
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NXP Semiconductors 15. Application information Table 58. Recommended bill of materials Designator Application C highly recommended for all bypass applications C highly recommended for all filter applications C mandatory for peripherals VBUS mandatory for host mandatory for OTG D recommended ...
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V BUS USB D+ STANDARD-B 4 GND RECEPTACLE A1 IP4359CX4/ ESD C VBUS C bypass Fig 29. Using the ISP1504x1 with a standard USB Peripheral Controller; external crystal V V CC(I/ ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS USB MICRO- RECEPTACLE 5 GND A1 IP4359CX4/ ESD C VBUS (1) Can be a square wave clock of ...
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V IN FAULT V BUS R pullup SWITCH ON OUT 1 V BUS USB D+ STANDARD-A 4 GND RECEPTACLE IP4359CX4/LF D ESD C VBUS Fig 31. Using the ISP1504x1 with a standard USB Host Controller; external ...
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NXP Semiconductors 16. Package outline TFBGA36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm ball A1 index area 1 ball A1 1 index area ...
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NXP Semiconductors 17. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 17.1 Introduction to soldering Soldering ...
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NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 61. Acronym ASIC ATX EOP ESR FS HBM HNP ...
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NXP Semiconductors Table 61. Acronym SOF SRP SYNC TTL TXCMD USB USB-IF ULPI UTMI UTMI+ [1] Physical layer containing the USB transceiver. The ISP1504x1 is a PHY. 19. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to ...
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NXP Semiconductors 21. Legal information 21.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Table 57. Dynamic characteristics: analog I/O pins DP and ...
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NXP Semiconductors 24. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration ...
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NXP Semiconductors 25. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 10.1 Immediate register set . . . . . . . . . . . . . . . . . . 48 10.1.1 Vendor ID and Product ID registers . . . . . . . . ...