AD9957BSVZ Analog Devices Inc, AD9957BSVZ Datasheet - Page 19

• Manufacturer Part Number: AD9957BSVZ
• Description: IC DDS 1GSPS 14BIT IQ 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9957BSVZ

• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Frequency Range: 60MHz To 1GHz
• Rf Type: Quadrature
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465
• Rf Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 100
• Mounting: Surface Mount
• Case Height: 1mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9957/PCBZ - BOARD EVAL AD9957 QUADRATURE MOD
• Lead Free Status / Rohs Status: Compliant

INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in interpolating DAC
mode is shown in Figure 28; grayed items are inactive. In this
mode, the Q data path, DDS, and modulator are all disabled; only
the I data path is active.
As in quadrature modulation mode, the PDCLK pin functions
as a clock, synchronizing the input of data to the AD9957.
TxENABLE
PDCLK
I/Q IN
FTW
18
PW
TIMING AND CONTROL
PROGRAMMING
PARALLEL DATA
REGISTERS
3
18
16
18
16
QS
Q
I
IS
SERIAL I/O
PORT
INTERNAL CLOCK TIMING AND CONTROL
Figure 28. Interpolating DAC Mode
I Q
RAM
IS QS
Rev. B | Page 19 of 64
OSK
AD9957
cos (ωt+θ)
θ
ω
sin (ωt+θ)
CLOCK
CONTROL
DDS
POWER
DOWN
No modulation takes place in the interpolating DAC mode;
therefore, the spectrum of the data supplied at the parallel port
remains at baseband. However, a sample rate conversion takes
place based on the programmed interpolation rate. The inter-
polation hardware processes the signal, effectively performing
an oversample with a zero-stuffing operation. The original
input spectrum remains intact and the images that otherwise
would occur from the sample rate conversion process are
suppressed by the interpolation signal chain.
2
2
SYSCLK
DAC GAIN
PLL
÷2
8
OUTPUT
FACTOR
SCALE
8-BIT
AUX
DAC
14-BIT
DAC
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
XTAL_SEL
AD9957