PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 52
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PSB2186N-V11TR
Manufacturer Part Number
PSB2186N-V11TR
Description
IC ISDN SUBSCRIB ACCESS 44-PLCC
Manufacturer
Infineon Technologies
Datasheet
1.PSB2186N-V11TR.pdf
(240 pages)
Specifications of PSB2186N-V11TR
Controller Type
Subscriber Access Controller (ISDN)
Interface
4-Wire SPI Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
17mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
PSB2186N-V11INTR
PSB2186N-V11TR
PSB2186N-V11TR
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2.4.5.3
In power down state, (see chapter 3.3.1) only an analog level detector is active. All clocks,
including the IOM interface, are stopped. The data lines are "high", whereas the clocks are
"low".
An activation initiated from the exchange side (Info 2 on S bus detected) will have the
consequence that a clock signal is provided automatically.
From the terminal side an activation must be started by setting and resetting the SPU bit in the
SPCR register (see chapter 4).
2.4.6
The transmit and receive bit clocks are derived, with the help of the DPLL, from the S-interface
receive data stream. The received signal is sampled several times inside the derived receive
clock period, and a majority logic is used to additionally reduce bit error rate in severe
conditions (see chapter 2.4.5). The transmit frame is shifted by two bits with respect to the
received frame.
The output clocks (DCL, FSC1 etc.) are synchronous to the S-interface timing.
Figure 29
Clock System of the ISAC
Semiconductor Group
Level Detection Power Down
Timing Recovery
®
-S TE in TE Mode
TE Mode
PLL
52
ITS05425
Functional Description
BCL
DCL
FSC
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