PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 149

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

4.1.6
Value after reset: 00
Note:
RMC
RRES
RNR
STI
XTF
XIF
Semiconductor Group
7
The maximum time between writing to the CMDR register and the execution of the
command is 2.5 DCL-clock cycles. During this time no further commands should be
written to the CMDR register to avoid any loss of commands.
Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the processor confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFO may be released.
Receiver Reset
HDLC receiver is reset, the RFIFO is cleared of any data.
In addition, in auto-mode, the transmit and receive counters (V(S), V(R)) are reset
Receiver Not Ready
Used in auto-mode only.
Determines the state of the ISAC-S TE HDLC receiver.
When RNR = "0", a received I or S-frame is acknowledged by an RR supervisory
frame, otherwise by an RNR supervisory frame.
Start Timer
The ISAC-S TE hardware timer is started when STI is set to one. In the internal timer
mode (TMD bit, MODE register) an S command (RR, RNR) with poll bit set is
transmitted in addition. The timer may be stopped by a write of the TIMR register.
Transmit Transparent Frame
After having written up to 32 bytes in the XFIFO, the processor initiates the
transmission of a transparent frame by setting this bit to "1". The opening flag is
automatically added to the message by the ISAC-S TE.
Transmit I Frame
Used in auto-mode only
After having written up to 32 bytes in the XFIFO, the processor initiates the
transmission of an I frame by setting this bit to "1". The opening flag, the address and
the control field are automatically added by the ISAC-S TE.
Command Register
RMC
RRES
H
RNR
STI
149
XTF
CMDR
XIF
Write
XME
Register Description
XRES
Address 21
0
H