PSB2186N-V11TR Infineon Technologies, PSB2186N-V11TR Datasheet - Page 229

• Manufacturer Part Number: PSB2186N-V11TR
• Description: IC ISDN SUBSCRIB ACCESS 44-PLCC
• Manufacturer: Infineon Technologies

Specifications of PSB2186N-V11TR

• Controller Type: Subscriber Access Controller (ISDN)
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 17mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PSB2186N-V11INTR; PSB2186N-V11TR

/***************************************************************************/
/*
/*
/*
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/*
/***************************************************************************/
EXPORT int
EnaClk_SBC (pt)
{
Semiconductor Group
/* Variables
/* =========
/* Function Declaration
/* ====================
register PEITAB
unsigned int
BYTE
BitSet = inp (pt->pt_r_star) & STAR_BVS;
count = 0;
for (i = 0; i < 500; i++)
Function: EnaClk_SBC ()
Parms
purpose : enable clocks for TE configurations
if ((inp(pt->pt_r_star) & STAR_BVS) != BitSet)
{
if (++count > 6)
i = 0;
BitSet = inp (pt->pt_r_star) & STAR_BVS;
}
return (FALSE);
: pointer to PEITAB table element
count, i = 0;
BitSet, spcr;
*pt;
/* Test to see if clocks are
/* actually there. Because the SBC
/* after reset does not deactivate
/* its clocks immediately we will
/* make pretty sure that the clocks */
/* are there before we leave this
/* routine
/* we test to see if 6 changes in
/* the STAR:BVS bit indicating the
/* reception of at least 3 frames
/* (6 B channels). If at any time
/* we fail to find a bit change
/* and the counter i reaches its
/* maximum then we assume that
/* clocks are no longer present
/* Of course we have to reset our
/* counter every time a bit change
/* is observed to give the next
/* bit change the same amount of
/* time in which to occur !!!
/* the Bx versions reqire one edge
/* at FSC.
/* Otherwise the setting of the SPU */
/* has no effect (result: no clock) */
/* The IOM direction control bit
/* IDC in the ADF1 (SQXR) register
/* is set before and reset after
/* the system is clocking
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Low Level Controller
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