DP83840AVCE National Semiconductor, DP83840AVCE Datasheet - Page 44

• Manufacturer Part Number: DP83840AVCE
• Description: IC ETHERNET PHYS LAYER 100-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83840AVCE

• Controller Type: Ethernet Controller, 10Base-T
• Interface: IEEE 802.3af
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 335mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83840AVCE

Version A
4.0 Registers
4.2 BASIC MODE CONTROL REGISTER (BMCR) (Continued)
4.3 BASIC MODE STATUS REGISTER (BMSR)
Address 00h
Address 01h
6:0
Bit
Bit
10
15
14
13
9
8
7
100BASE-TX Half
100BASE-TX Full
Restart Auto-Ne-
Collision Test
Duplex Mode
100BASE-T4
Bit Name
Bit Name
Reserved
gotiation
Duplex
Duplex
Isolate
(Continued)
(PHYAD = 00000),
0, RW/SC
0, RO/P
1, RO/P
1, RO/P
Default
Default
1, RW
0, RW
X, RO
RW
ISOLATE:
1 = Isolates the DP83840A from the MII with the exception of the serial
0 =Normal Operation
If the PHY Address is set to 00000 the Isolate bit will be set upon power-
up/reset. Refer to section 3.2.4 for further detail.
RESTART AUTO-NEGOTIATION:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process.
0 = Normal Operation
Refer to section 3.9.4 for further detail.
DUPLEX MODE:
1 = Full Duplex operation. Duplex selection is allowed when Auto-
0 = Half Duplex Operation
COLLISION TEST:
1 = Collision Test enabled. When set, this bit will cause the COL signal
to be asserted in response to the assertion of TX_EN.
0 = Normal Operation
RESERVED: Write as 0, read as don't care.
100BASE-T4 CAPABLE:
1 = DP83840A able to perform in 100BASE-T4 mode
0 = DP83840A not able to perform in 100BASE-T4 mode
100BASE-TX FULL DUPLEX CAPABLE:
1 = DP83840A able to perform 100BASE-TX in full duplex mode
0 = DP83840A not able to perform 100BASE-TX in full duplex mode
100BASE-TX HALF DUPLEX CAPABLE:
1 = DP83840A able to perform 100BASE-TX in half duplex mode
0 = DP83840A not able to perform 100BASE-TX in half duplex mode
If Auto-Negotiation is disabled (bit 12 of this register cleared), this bit
has no function. This bit is self-clearing and will return a value of 1
until Auto-Negotiation is initiated by the DP83840A, whereupon it will
self-clear. Operation of the Auto-Negotiation process is not affected
by the management entity clearing this bit.
Negotiation is disabled (bit 12 of this register is cleared). When Auto-
Negotiation is enabled, the duplex capability as specified in bits
[15:11] of the BMSR register (address 1h) reflect the current status.
This bit does not reflect duplex status.
management. When this bit is asserted, the DP83840A does not
respond to TXD[3:0], TX_EN, and TX_ER inputs, and it presents a
high impedance on its
RXD[3:0], COL and CRS outputs. The CLK_25M output stays active
(if enabled) and the DP83840A still responds to serial management
transactions. During Isolate mode TX_EN has no effect, TD+/- will
transmit Idles, TXU+/- and TXS+/- will tri-state, transitions on the
receive inputs RD +/- and RXI +/- are ignored, and link is disabled.
44
National Semiconductor
Description
Description
TX_CLK, RX_CLK, RX_DV, RX_ER,