DP83840AVCE National Semiconductor, DP83840AVCE Datasheet
DP83840AVCE
Specifications of DP83840AVCE
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DP83840AVCE Summary of contents
Page 1
... Independent Interface (MII), ensuring interoperability between products from different vendors. The DP83840A is designed with National Semiconductor's BiCMOS process. Its system architecture is based on the integration of several of National Semiconductor's industry proven core technologies: 10BASE-T ENDEC/Transceiver module to provide the 10 Mb/s IEEE 802.3 functions Clock Recovery/Generator Modules from National ...
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... INJECTION SCRAMBLER 10BASE-T PARALLEL TO SERIAL TX UTP/STP NRZ / NRZI AUTO NEGOTIATION 100BASE-X 10 BASE-T INTERFACE 2 MII 100 Mb/s RECEIVE RX STATE MACHINE PCS SSD DETECT CARRIER SENSE COLLISION DETECTION CODE-GROUP DECODER CODE-GROUP ALIGNMENT DESCRAMBLER RX SERIAL TO PARALLEL NRZI TO NRZ CRM 100BASE-X RECEIVE INTERFACE National Semiconductor ...
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... DC Specifications 8.3 Clock Timing 8.4 MII Serial Management AC Timing 8.5 100 Mb/s AC Timing 8.6 10 Mb/s AC Timing 8.7 Fast Link Pulse Timing 8.8 Clock Recovery Module Timing 8.9 Reset Timing 8.10 Loopback Timing 8.11 PHY Isolation Timing 9.0 Package Dimensions 3 National Semiconductor ...
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... RXI+ TDV TXS- TXS+ 24 TXU- 25 TXU TDGND RTX 28 REQ 29 PLLGND FIGURE 1. DP83840A Pin Connection Diagram Version DP83840AVCE 10/100BASE-X ETHERNET PHYSICAL LAYER 100 -PIN JEDEC METRIC PQFP National Semiconductor 4 Subject to change without notice IOGND6 IOV 79 CC6 78 TXD[0] 77 TXD[1] 76 TXD[2] 75 TXD[3] 74 TX_EN 73 ...
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... The maximum clock rate is 2.5 MHz. There is no minimum clock rate. MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5k pullup resistor TRI-STATE output J = IEEE 1149.1 pin 5 National Semiconductor Subject to change without notice. ...
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... This pin can be used to drive peripheral circuitry such as an LED indicator or control circuits for common magnetics. This is also the PHY address sensing (PHYAD[3]) pin for multiple PHY applications- -see Section 2.8 for more details TRI-STATE output J = IEEE 1149.1 pin 6 National Semiconductor ...
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... SHIELDED TWISTED PAIR OUTPUT: This differential output pair sources the 10BASE-T transmit data and link pulses for STP cable. TWISTED PAIR RECEIVE INPUT: These are the differential 10BASE-T receive data inputs for either STP or UTP TRI-STATE output J = IEEE 1149.1 pin 7 National Semiconductor ...
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... Used for 10BASE-T timing and Auto-Negotiation. If not used, this pin should be pulled (4.7 k pull up resistor suggested). When pulled high, the CC. DP83840A detects this condition, enables the internal 2.5 divider, and switches the 10 Mb/s and Auto-Negotiation circuitry to the internally derived 20 MHz clock TRI-STATE output J = IEEE 1149.1 pin 8 0.005 stal National Semiconductor ...
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... CIM requirements. At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4 latched to bit 12 of the PCS Configuration Register, address 17h TRI-STATE output J = IEEE 1149.1 pin 9 (1), a continuous 25 MHz clock (C Forced Mode Advertised Mode (1), a continuous CC National Semiconductor ...
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... COL) remain active and unaffected by this bypass mode. Refer to figures 4 and 5. At power-up/reset, the value on this pin (set by a pull-up or pull-down resistor, typically 4 latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register at address 18h TRI-STATE output J = IEEE 1149.1 pin 10 National Semiconductor ...
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... Mb/s and 100 Mb/s operation. COLLISION LED: Indicates the presence of collision activity for 10 Mb/s and 100 Mb/s Half Duplex operation. This LED has no meaning for 10 Mb/s or 100 Mb/s Full Duplex operation and will remain deasserted. Active low TRI-STATE output J = IEEE 1149.1 pin 11 National Semiconductor ...
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... TEST CLOCK: Test clock for the IEEE 1149.1 circuitry. If Boundary-Scan is not implemented this pin may be left unconnected (NC). TEST MODE SELECT: Control input to the IEEE 1149.1 test circuitry. If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since it has an internal pull-up resistor ( TRI-STATE output J = IEEE 1149.1 pin 12 National Semiconductor ...
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... RESET: Active high input that initializes or reinitializes the DP83840A. See section 3.10 for further detail. LOW POWER MODE SELECT: Active high input that enables the low power mode (100 Mb/s operation only). See section 3.13 for further detail TRI-STATE output J = IEEE 1149.1 pin 13 National Semiconductor ...
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... For future upgradability, connect this pin to GND via a 0 resistor. RESERVED_0: These pins are reserved for future use. These pins must be connected to ground. For future upgradability, connect these pins to GND via 0 resistors TRI-STATE output J = IEEE 1149.1 pin 14 National Semiconductor ...
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... For 100 Mb/s operation, the MII operates in nibble mode with a clock rate of 25 MHz. This clock rate is independent of bypass conditions. In normal (non-bypassed) operation the MII data at RXD[3:0] and TXD[3:0] is nibble wide. In bypass mode (BP_4B5B or BP_ALIGN set) the MII data takes the form of National Semiconductor 15 ...
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... Register Address TA (00h = BMCR) FIGURE 3. Typical MDC/MDIO Write Operation Table I. <idle><01><10><AAAAA> <RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> <idle><01><01><AAAAA> <RRRRR><10><xxxx xxxx xxxx xxxx><idle> Register Data Idle Register Data Idle National Semiconductor ...
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... IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable). 3.3.3 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 17 transmitter provides flexibility National Semiconductor for ...
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... This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 s period, the entire descrambler will be forced out used to constantly monitor National Semiconductor the ...
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... FROM CGM BYP_4B5B BYP_SCR BYP_ALIGN _NRZI_EN Version A (Continued) TX_CLK TXD[3:0] CODE-GROUP ENCODER MUX SCRAMBLER MUX MUX PARALLEL TO SERIAL NRZ TO NRZI ENCODER MUX 100BASE-X LOOPBACK TD +/- FIGURE 4. 100BASE-X Transmitter 19 100 Mb/s TX STATE MACHINE FAR END FAULT INDICATION CARRIER SENSE COLLISON DETECTION National Semiconductor ...
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... MII 4B Nibble Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 National Semiconductor ...
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... ALIGNMENT MUX DESCRAMBLER SERIAL TO PARALLEL MUX NRZI TO NRZ DECODER DATA CLK CLOCK RECOVERY MODULE RD +/- FIGURE 5. 100BASE-X Receiver 21 CARRIER INTEGRITY MONITOR LINK INTEGRITY MONITOR FAR END FAULT INDICATION 100 Mb/s RX STATE MACHINE RX_DATA VALID SSD DETECT CARRIER SENSE COLLISON DETECTION National Semiconductor ...
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... Auto-Negotiation provides a mechanism for transferring information from the Local Station to the Link Partner that a remote fault has occurred for 100BASE-TX. As Auto- Negotiation is not currently specified for operation over fiber, the Far End Fault Indication function (FEFI) provides this capability for 100BASE-FX applications. 22 National Semiconductor ...
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... This option is shown in Figure 9. Because the CLK25M output is not used with this clocking scheme recommended that it be disabled by setting bit 7 of the PCS Configuration Register (PCR address 17h). 23 (4.7 k pull-up resistor recommended)). from the integrated 10BASE-T National Semiconductor ...
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... DP83840A DIV 2.5 OSCIN DIV 2.0 CLK25M REFIN 25 MHz TO 100 Mb/s SECTION TX_CLK 25 MHz FROM 100 Mb/s SECTION MUX 2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION SPEED SELECT FIGURE 6. Single 50 MHz Reference 24 20 MHz TO 10 Mb/s SECTION National Semiconductor ...
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... MHz TO 10 Mb/s SECTION 25 MHz TO 100 Mb/s SECTION 25 MHz FROM 100 Mb/s SECTION 2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION 20 MHz TO 10 Mb/s SECTION 25 MHz TO 100 Mb/s SECTION 25 MHz FROM 100 Mb/s SECTION 2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION National Semiconductor ...
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... FIGURE 10. Single 25 MHz Reference 26 20 MHz TO 10 Mb/s SECTION 25 MHz TO 100 Mb/s SECTION 25 MHz FROM 100 Mb/s SECTION 2.5 MHz (OR 10 MHz) FROM 10 Mb/s SECTION TO 10 Mb/s SECTION DIV 2.5 25 MHz TO 100 Mb/s SECTION 25 MHz FROM 100 Mb/s SECTION FROM 10 Mb/s SECTION National Semiconductor ...
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... The example provided in Figure 12 illustrates interconnection only and should not be considered as a reference design. RXD MAC PHY RX_CLK TD TXD RD TX_CLK 50 MHz ENDEC 25 MHz (DP83850 100RIC) RX_CLK DP83840A (2) DP83223 (2) 27 PMD DP83840A (12) DP83223 (12) National Semiconductor ...
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... SQE is reported as a pulse on the COL signal of the MII. 3.7.5 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activity once valid data is detected via the Smart Squelch function. 28 and transmit channels are National Semiconductor active ...
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... Functional Description TXD TXE LOOPBACK COL TXC CRS RXD RXC RESET FIGURE 13. 10BASE-T Transceiver Block Diagram Version A (Continued) 29 PLLGND REQ RTX TDGND TXU_PLUS TXU_MINUS TXS_PLUS TXS_MINUS TDVCC RXI_PLUS RXI_MINUS RXGND RXVCC National Semiconductor ...
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... Encoder/Decoder (ENDEC) Module The Endec Module consists of essentially four functions: The oscillator generates the 10 MHz transmit clock signal for system timing from a 20 MHz oscillator. 30 10BASE-T Transceiver Module the required signal conditioning transformers and impedance National Semiconductor is ...
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... FIGURE 14. 10BASE-T Twisted Pair Smart Squelch Operation 20 MHz (50ppm) Version A (Continued) Twisted Pair Squelch Operation (OSCIN) (OSCOUT Alternatively, a 20MHz crystal (with nominal 12pF loading) can be utilized in place of the oscillator. When not used, X1 should be pulled-up to Vcc (4.7k recommended). FIGURE 15. X1 and X2 Oscillator Module 31 National Semiconductor ...
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... Fixed Current Source RTX Fixed Current Source REQ FIGURE 16. REQ and RTX Operation 32 for these to 10%. Again, experimentation Transmit Amplitude Control Transmit Pre-emphasis Control National Semiconductor is ...
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... F 1% 49.9 0. 0.01 F (For STP applications, the RXI+/- termination resistors should each be 75 +/-1%) FIGURE 17. Typical 10BASE-T Node Application LOW CURRENT LEDS 1:2 10BASE-T INTERFACE TD+ TD- RD+ RD- 1:1 RJ45 National Semiconductor ...
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... Repeating the test with the inverse bit pattern provides coverage 3.8.3 Boundary Scan Description Language File A Boundary Scan Description Language (BSDL) file is available. Contact your local National Semiconductor representative to obtain the latest version. 34 and GND short/open circuits. National Semiconductor ...
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... TMS TCK CONTROLER TRST Version A (Continued) CORE LOGIC DATA MUX PAD LOGIC INSTR. PRELOAD INSTR. REGISTER INSTR. REGISTER AND IR-CLOCKS DR CLOCK GATING LOGIC DR-CLOCKS SELECT TAP ~TCK ENABLE FIGURE 18. TIEEE 1149.1 Architecture 35 TDO DRIVER DI MUX TDO DATA REGISTER SELECT National Semiconductor ...
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... The Speed Selection and Duplex Mode bits have no effect on the mode of operation when the Auto-Negotiation Enable bit (bit 12, register address 00h) is set OUT MHz 25 MHz C National Semiconductor OUT ...
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... Duplex and 10BASE- T Full Duplex Available Auto-Negotiation Enabled with 100BASE-X Half- Duplex and 10BASE-T Half Duplex Available Auto-Negotiation Enabled with 100BASE-X Full- Duplex and 100BASE-X Half Duplex Available Auto-Negotiation Enabled with 10BASE-T Full- Duplex and 10BASE-T Half Duplex Available 37 Mode National Semiconductor ...
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... Basic Mode Control Register (address 00h) must first be cleared and then set for any auto-negotiation function to take effect. 38 and link pulse activity until National Semiconductor the ...
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... Driver code should wait 500 s following a software reset before allowing further serial MII ramp CC operations with the DP83840A. 39 ramp reached 4V. CC Latched in at Reset PHYAD[0] PHYAD[1] PHYAD[2] PHYAD[3] PHYAD[4] AN0 AN1 REPEATER 10BTSER BPALIGN BP4B5B BPSCR National Semiconductor ...
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... DP83840A is in either node mode or repeater mode with the only difference being CRS functionality “translational” mode, if the DP83840A is configured for repeater operation, the CRS signal will be suppressed during transmit such that only actual network collisions will be flagged. 40 National Semiconductor ...
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... The selection between the two modes is determined by the state of the LOWPWR pin (pin 3). When LOWPWR is high, the low power mode is selected. When LOWPWR is low, full functionality of the DP83840A is available. Version A for serial/parallel via MII serial 41 National Semiconductor ...
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... Loopback, Bypass and Receiver Error Mask Register PHY Address Register Reserved for PHY Specific Future Assignment by Vendor 10BASE-T Status Register 10BASE-T Configuration Register Reserved for Future Use--Do Not Read/Write to These Registers <access type> Read Only RW = Read/Write <attribute(s)> Latching SC = Self Clearing P = Value Permanently Set 42 National Semiconductor ...
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... This bit is intended only to control the state of Auto-Negotiation and should not be regarded as status. Refer to section3.9.2 for further detail. RESERVED: Write as 0, read as don’t care. National Semiconductor 43 ...
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... DP83840A able to perform 100BASE-TX in full duplex mode 0 = DP83840A not able to perform 100BASE-TX in full duplex mode 100BASE-TX HALF DUPLEX CAPABLE DP83840A able to perform 100BASE-TX in half duplex mode 0 = DP83840A not able to perform 100BASE-TX in half duplex mode 44 Description TX_CLK, RX_CLK, RX_DV, RX_ER, Description National Semiconductor ...
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... Jabber condition detected Jabber This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this register by the management interface DP83840A reset. This bit only has meaning in 10 Mb/s mode. National Semiconductor 45 ...
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... Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National Semiconductor's IEEE assigned OUI is 080017h. Bit Bit Name ...
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... Full Duplex not supported 10BASE-T SUPPORT 10BASE-T is supported by the local device 0 = 10BASE-T not supported PROTOCOL SELECTION BITS: These bits contain the binary encoded protocol selector supported by this node. RW <00001> indicates that this device supports IEEE 802.3 CSMA/CD 47 Description National Semiconductor ...
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... FULL DUPLEX SUPPORT 10BASE-T Full Duplex is supported by the Link Partner 0 = 10BASE-T Full Duplex not supported by the Link Partner 10BASE-T SUPPORT 10BASE-T is supported by the Link Partner 0 = 10BASE-T not supported by the Link Partner PROTOCOL SELECTION BITS: Link Partner's binary encoded protocol selector Description National Semiconductor ...
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... J/K symbol detection. This counter freezes when full (at FFFFh). This counter represents the total number of false carrier events since the last management read. The Carrier Integrity Monitor uses its own counter to qualify whether the link is unstable. National Semiconductor 49 ...
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... In node mode, and not configured for Full Duplex operation, CRS is asserted due to either receive or transmit activity. The value of the REPEATER pin 47 (set by a pull-up or pull-down resistor, typically 4 latched into this bit at power-up/reset. National Semiconductor 50 s supports 100BASE-X switch/router ...
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... Normal LED1 operation--10 Mb/s and 100 Mb/s transmission activity LED4 MODE SELECT LED4 output (pin 37) configured to indicate Full Duplex mode status for 10 Mb/s and 100 Mb/s operation 0 = LED4 output configured to indicate Polarity in 10BASE-T mode or Full Duplex in 100BASE-TX mode RESERVED: Write as 0, read as don't care. National Semiconductor 51 ...
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... BMCR bit 14 (address 00h), will produce a “dead time” of 550 s before any valid data appears at the TD+/- or RXD[3:0] outputs. BMCR bit 14, if set, take precedence over LB1 and LB0. Refer to section 3.11 for further detail. RESERVED: Write as 0, read as don't care. National Semiconductor 52 mode such that ...
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... Data is passed to RXD[3:0] unchanged and with RX_ER set to 0 PACKET ERRORS Forces packet errors (722 s timeout reported with the value 2h on RXD[3:0] and with RX_ER set Data is passed to RXD[3:0] unchanged and with RX_ER set to 0 RESERVED: Write as 0, read as don't care. National Semiconductor 53 ...
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... CARRIER INTEGRITY MONITOR STATUS: This bit indicates the status of the Carrier Integrity Monitor function. This status is optionally muxed out through the LED1 pin when the LED1_MODE register bit (bit 2 of the PCR, address 17h) is asserted Unstable link condition detected 0 = Unstable link condition not detected National Semiconductor 54 ...
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... The first PHY address bit transmitted or received over the serial MII is the MSB of the address (bit 4). A station management entity must know the address of each PHY it is connected to in order to gain access. A PHY address of <00000> will cause the Isolate bit of the BMCR (bit 10, register address 00h set. National Semiconductor 55 ...
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... The pair that is not selected will tri-state. LOW SQUELCH SELECT: Selects between standard 10BASE-T receiver squelch threshold and a reduced squelch threshold that is useful for longer cable applications and/or STP operation Low Squelch Threshold selected 0 = Normal 10BASE-T Squelch Threshold selected RESERVED: Write as 0, read as don't care. National Semiconductor 56 ...
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... Description JABBER ENABLE: Enables or disables the Jabber function when the DP83840A is in 10BASE-T Full Duplex or 10BASE-T Transceiver Loopback mode (10BT_LPBK bit 11 in the LBREMR, address 18h Jabber function enabled 0 = Jabber function disabled This bit has no meaning in 100 Mb/s mode. 57 National Semiconductor ...
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... It is not intended full circuit diagram. For detailed system level application information please contact your National Semiconductor sales representative. 5.2 PLANE PARTITIONING The recommendations for power plane partitioning provided herein represent a more simplified approach when compared to earlier recommendations ...
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... DP83223 System Ground DP83840A DP83223 System Ground System VCC DP83840A DP83223 System VCC Signal Routing DP83840A DP83223 FIGURE 21. Power and Ground Plane Isolation 59 Chassis Ground Magnetics RJ45 Signal Routing Magnetics RJ45 Signal Routing Magnetics RJ45 Chassis Ground Magnetics RJ45 National Semiconductor ...
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... FIGURE 22. DP83840A Power Supply Decoupling and Isolation Version A 10UF 0.01UF 0.01UF DP83840A 4 FB 10UF ALL CAPS ARE 16V CERAMIC ALL RESISTORS ARE 1/8WATT, 5% TOLERANCE = FERRITE BEAD MURATA # BLM31A02PT OR TDK # TDK-ACB1608M-080 60 VCC IOGND2 IOVCC2 OGND OVCC PLLVCC 10UF 0.01UF VCC 0.01UF GND National Semiconductor 0.01UF FB 10 ...
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... PHY address. This, in turn, will impair serial MII management of the PDP83840A. 61 National Semiconductor ...
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... All resistors are 1/8th Watt, +/- 5% tolerance 4.7k TXREF Q1 1.2 k 1.2 k GND 1.0 k All resistors are 1/8th Watt, +/- 5% tolerance 1.2k TXO+ Term TXREF Q1 Q2 100 100 62 used for Common Magnetics per IEEE 802.3u/D5.3 section TXO+ Term TXO- Term Q3 Q2 1.2 k TXO- Term Q3 100 ue National Semiconductor ...
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... Symptoms: National Semiconductor believes that there will be no system ramifications with higher than specified Vod voltages. The worse case scenario would be a slight increase in cross-talk in between the twisted pair cables. ...
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... DP83840A’s that have return loss in the range of 4-6dB, and did not see any degradation in system performance. Solution/Workaround: To improve the return loss at idle, National Semiconductor recommends that 1000pF capacitors be place in parallel to the 10.5 termination resistors connected to the TXU+/- pins ...
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... DP83840A receives an extra ‘erroneous’ pulse, then it will take a few additional FLP bursts to set the ACK bit. Issue 4: The link_fail_inhibit_timer is used to give the link a chance to become good once a technology is selected. The DP83840A will National Semiconductor 65 inter-group gap greater than break_link_timer expires, ...
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... Solution/Workaround: There are no plans on fixing any of the issues on the DP83840A. We will incorporate changes to fix the above issues in future products to insure our products a specification compliant. Version A (Continued) National Semiconductor 66 ...
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... Negotiation will take to complete is under 3 seconds. Therefore, the proposed software driver should implement the following: Reset the 840A the DP83840A by writing 8000h to BMCR register, or re-start Auto-Negotiation by writing 1200h to BMCR register. Wait 3 seconds then read bit 5 (Auto- Negotiation Complete bit) and bit 2 (Link_Status bit) in the National Semiconductor 67 ...
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... When the DP83840A is put into 10 Mb/s repeater mode and receives a non-101010... jam pattern, Carrier Sense (CRS) will glitch during collision. This will cause problems when used in repeater applications where CRS is used to determine collisions. The collision signals from the DP83840A behave normally. National Semiconductor 68 be disabled when used ...
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... JAM signals, but there are a few MACs that will send out pseudo-random 5/10 MHz data. Solution/Workaround: Putting the part into Full-Duplex mode eliminates the CRS glitching problem. However, when the part is in Full-Duplex mode the COL pin (pin 65) will not indicate if collisions have occurred. FIGURE 27. CRS Glitching National Semiconductor 69 ...
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Electrical Specifications 8.0 Electrical Specifications 8.1 RATINGS AND OPERATING CONDITIONS 8.1.1 Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (DC ) OUT Storage Temperature ECL Signal Output Current ESD Protection 8.1.3 Thermal ...
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Electrical Specifications 8.2 DC Specifications Symbol Pin Types I I Input Low IL I/O Current I/O, Z (excluding RXI+/- and RD+/-) X1 Input TMS, TDI, TRST Inputs Output Low OL I/O Voltage I/ ...
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Electrical Specifications 8.2 DC Specifications Symbol Pin Types I I (ECL) Input Current INECL V O (ECL) Output High OHECL Voltage V O (ECL) Output Low OLECL Voltage I power Total Supply CC Current power Total Supply Current Version ...
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Electrical Specifications 8.3 CLOCK TIMING 8.3.1 Clock Reference and Clock Generation Timing Parameter Description T1 OSCIN to CLK25M Delay OSCIN = 50 MHz T2 CLK25M Rise Time T3 CLK25M Fall Time T4 OSCIN to TX_CLK Delay 10 Mb/s Operation ...
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Electrical Specifications 8.4 MII Serial Management Timing 8.4.1 MII Serial Management Timing Parameter Description T1 MDC to MDIO (Output) Delay Time T2 MDIO (Input) to MDC Set Time T3 MDIO (Input) to MDC Hold Time T4 MDC Frequency MDC ...
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Electrical Specifications 8.5 100 Mb/s AC Timing 8.5.1 100 Mb/s MII Transmit Timing Parameter Description T1 TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK TXD[4:0] Data Setup to TX_CLK TXD[4:0] Data Setup to TX_CLK T2 TXD[3:0], TX_EN, TX_ER Data Hold ...
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Electrical Specifications 8.5.2 100 Mb/s MII Receive Timing Parameter Description T1 RX_EN to RX_CLK, RXD[3:0], RX_ER, RX_DV Active T2 RX_EN to RX_CLK, RXD[3:0], RX_ER, RX_DV Tri-State T3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Translational RX_CLK to RXD[4:0], ...
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Electrical Specifications 8.5.3 100 Mb/s Transmit Packet Timing Parameter Description T1 TX_CLK to TD+/- Latency Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first ...
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Electrical Specifications 8.5.5 100 Mb/s Receive Packet Timing Parameter Description T1 Carrier Sense on Delay T2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group ...
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Electrical Specifications 8.6 10 Mb/s AC Timing 8.6.1 10 Mb/s Transmit Timing (Start of Packet) Parameter Description T1 Transmit Enable Setup Time from the Rising Edge of TXC T2 Transmit Data Setup Time from the Rising Edge of TXC ...
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Electrical Specifications 8.6.2 10 Mb/s Transmit Timing (End of Packet) Parameter Description T1 Transmit Enable Hold Time from Rising Edge of TX_CLK T2 End of Packet High Time (with ‘0’ ending bit) T3 End of Packet High Time (with ...
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Electrical Specifications 8.6.3 10 Mb/s Receive Timing (Start of Packet) Parameter Description T1 Carrier Sense Turn On Delay (RXI+/- to CRS) T2 Decoder Acquisition Time T3 Receive Data Latency T4 SFD Latency T5 RX_CLK to RXD Delay Time Note: ...
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Electrical Specifications 8.6.4 10 Mb/s Receive Timing (End of Packet) Parameter Description T1 Carrier Sense Turn Off Delay Note: The de-assertion of CRS is asynchronous and is therefore not directly measured. RXI+/- RX_CLK CRS RXD RX_DV Version A (Continued) ...
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Electrical Specifications 8.6.5 Heartbeat Timing Parameter Description T1 CD Heartbeat Delay T2 CD Heartbeat Duration TXE TXC COL 8.6.6 10 Mb/s Jabber Timing Parameter Description T1 Jabber Activation Time T2 Jabber Deactivation Time TXE TD+/- COL Version A (Continued) ...
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Electrical Specifications 8.6.7 10BASE-T Normal Link Pulse Timing Parameter Description T1 Clock, Data Pulse Width T2 Clock Pulse to Clock Pulse Period 8.7 Auto-Negotiation Fast Link Pulse (FLP) Timing 8.7.1 Auto-Negotiation Fast Link Pulse (FLP) timing Parameter Description T1 ...
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Electrical Specifications 8.8 CRM (Clock Recovery Module) Timing 8.8.1 CRM Window Timing Parameter Description T1 CRM Sampling Window Note 1: The CRM Sampling Window is a measure of the PLL‘s ability to recover data even with a high degree ...
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Electrical Specifications 8.9 Reset Timing 8.9.1 Hardware Reset Timing Parameter Description T1 Internal Reset Time T2 Hardware RESET Pulse Width T3 Post Reset Stabilization time prior to MDC preamble for register accesses T4 Hardware Configuration Latch- in Time from ...
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Electrical Specifications 8.10 Loopback Timing 8.10.1 10 Mb/s and 100 Mb/s Loopback Timing Parameter Description T1 TX_EN to RX_DV Loopback Note 1: The 100BASE-X PMD Loopback option timing is dependent on the external transceiver loopback timing and is therefore ...
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Electrical Specifications 8.10.2 Remote Loopback Parameter Description T1 Remote Loopback RD+/- TD+/- 8.11 Isolation Timing 8.11.1 PHY Isolation Timing Parameter Description T1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal ...
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... National Semiconductor Corporation Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408 89 National Semiconductor Corporation Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 ...