LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 80

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Revision 1.4 (12-17-08)
3.7.5.1
3.7.6
MAC Wakeup
PHY Interrupt
Event
CONDITION
T5 (D3RST)
T10, T11
T1, T3
T9
T6
Note 3.10 PHY register bits designated as NASR are not initialized by setting the
Note 3.11 PHY reset conditions and mode settings are discussed in
PHY Resets
In addition to the PHY_RST, PHY_SRST and PCInRST noted in
on specific state transitions depending on the state of the VAUXDET signal and
(PME_EN)
leave the PHY in normal operating mode (all-capable with auto-negotiation enabled) or in the General
Power-Down mode. Specific PHY reset conditions and the state of the PHY following reset, are
detailed in
3.7.4, "Power States," on page
Detecting Power Management Events
LAN9420/LAN9420i supports the ability to generate PCI wake events using nPME on detection of a
Magic Packet, Wakeup Frame or Ethernet link status change (energy detect). A simplified diagram of
the wake event detection logic is shown in
(PMT_CTRL Register)
(PMT_CTRL Register)
(PMT_CTRL Register)
(PMT_CTRL Register)
Table 3.23
bit in the
in the PHY’s
on page 80
WUPS[1]
WUPS[0]
WOL_EN
ED_EN
RW
RW
Figure 3.29 Wake Event Detection Block Diagram
VAUXDET
PCI Power Management Control and Status Register
below. The state transitions noted in this table refer to those specified in
X
X
0
1
1
Basic Control
75.
Table 3.23 PHY Resets
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
Register.
80
Figure
PME_EN
(PCI_PMCSR Register)
(PCI_PMCSR Register)
X
X
0
0
0
PME_STATUS
3.29.
PME_EN
RW
Table
3.22, the PHY may also be reset
Section 3.7.5.1, "PHY Resets,"
General Power-Down
General Power-Down
General Power-Down
(PCI_PMCSR). Resets may
SMSC LAN9420/LAN9420i
Normal
Normal
MODE
PHY Soft Reset
(Interrupt Controller)
(PCI Bus)
PME Enable
WAKE_INT
nPME
Datasheet
Section
bit