LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 46

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Revision 1.4 (12-17-08)
30:16
14:12
BITS
31
15
10
11
9
Transmit Descriptor 0 (TDES0)
TDES0 contains the transmitted frame status and the descriptor ownership information.
OWN - Own Bit
When set, indicates that the descriptor block and associated buffer(s) are owned by the DMA
controller. When reset, indicates that the descriptor block and associated buffer(s) are owned by
the Host system.
Host Actions: Checks this bit to determine ownership of the descriptor block and associated
buffer(s). The Host sets this bit to pass ownership to the DMAC. The Host does not modify a
descriptor block or access its associated buffer(s) until this bit is cleared by DMAC or until the
DMAC is in STOPPED state, whichever comes first. The ownership bit of the first descriptor of the
frame should be set after all subsequent descriptors belonging to the same frame have been set.
This avoids a possible race condition between the DMA controller fetching a descriptor and the Host
setting an ownership bit.
DMAC Actions: Reads this bit to determine ownership of the descriptor block and its associated
buffer(s). The DMAC clears this bit either when it completes the frame transmission or when the
buffers that are associated with this descriptor are empty. By clearing this bit, the DMAC closes the
descriptor block and passes ownership to the Host. If the DMAC fetches a descriptor with the OWN
bit cleared, the DMAC state machine enters the SUSPENDED state.
RESERVED
Host Actions: Cleared on writes and ignored on reads.
DMAC Actions: Ignored on reads and cleared on writes.
ES - Error Summary
Indicates the logical OR of the following TDES0 bits:
TDES0[2] – Excessive Deferral
TDES0[8] – Excessive collisions
TDES0[9] – Late collision
TDES0[10] – No carrier
TDES0[11] – Loss of carrier
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
RESERVED
Host Actions: Cleared on writes and ignored on reads.
DMAC Actions: Ignored on reads and cleared on writes.
LC - Loss of Carrier
When set, indicates loss of carrier during transmission.
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
NC - No Carrier
When set, indicates that the carrier signal from the transceiver was not present during transmission.
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
LT - Late Collision
When set, indicates that the frame transmission was aborted due to collision occurring after the
collision window of 64 bytes.
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
Table 3.9 TDES0 Bit Fields
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
46
DESCRIPTION
SMSC LAN9420/LAN9420i
Datasheet