LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 77

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.7.4.3.2
3.7.4.4
3.7.4.4.1
3.7.4.4.2
detection. Refer to section
information.
EXITING THE D0
The device will exit the D0
Figure 3.28 on page
The D3
In this state the PCI power is on, but normal Ethernet receive and transmit operation is disabled. In
D3
(PME_EN)
power is also conserved by placing the internal PHY into General Power-Down mode on transition to
this state.
In D3
I/O accesses. While in this state, the
Management Control and Status Register (PCI_PMCSR)
POWER MANAGEMENT EVENTS IN D3
If configured to do so, the device is capable of detecting MAC (WOL, Magic Packet) and PHY (link
status change) wake events and is capable of asserting nPME as a result of detection. Refer to section
Section 3.7.6, "Detecting Power Management Events," on page 80
EXITING THE D3
The device will exit the D3
Figure 3.28 on page
HOT
D0
selects the “D3” state in the
Management Control and Status Register
VAUXDET=X, PWRGOOD=1). If the
Control and Status Register (PCI_PMCSR)
the General Power-Down mode on this transition. If
that the device will be required to detect Ethernet power management events and the PHY is not
reset or placed in General Power-Down mode.
D0
(PCInRST=1 to 0, PM_STATE=00b, VAUXDET=X, PWRGOOD=1).
D0
has been initialized and the
Management Control and Status Register (PCI_PMCSR)
turned off and 3.3Vaux is still operational (PCInRST=1, PM_STATE=00b, VAUXDET=1,
PWRGOOD=1 to 0).The internal PHY is reset and is placed in the General Power-Down mode on
this transition. Note that if VAUXDET=0, the device is being powered from the PCI +3.3V supply
and will turn off (G3) when PCI power is removed.
D0
PM_STATE=XXb, VAUXDET=1 to 0, PWRGOOD=1 to 0). For example, total power failure.
D3
by the Host system and then PCI power is turned off, but PCI 3.3Vaux remains operational
(PCInRST=X, PM_STATE=11b, VAUXDET=1, PWRGOOD=1 to 0). In this state the device is
powered by the PCI 3.3Vaux supply.
D3
selects the “D0” state in the
Management Control and Status Register (PCI_PMCSR)
VAUXDET=X, PWRGOOD=1). A D3 Transition Reset (D3RST) occurs during this transition. Refer
to
HOT
Section 3.7.5, "Resets," on page 79
A
A
A
A
HOT
HOT
power is reduced by disabling the internal PLL and derivative clocks. If the
to D3
to D3
to D0
to G3 (T12): This transition occurs when all power supplies are turned off (PCInRST=X,
HOT
PCI configuration accesses are permitted, but the device will not respond to PCI memory or
to D3
to D0
bit in the
COLD
State
HOT
U
(T7): This transition occurs when PCInRST is asserted while in the D0
COLD
U
A
HOT
(T3): This transition occurs when, during normal device operation, the Host system
(T5): This transition occurs when the device is in the D3
(T11): This transition occurs when all power supplies are operational and the device
STATE
75.
75.
PCI Power Management Control and Status Register (PCI_PMCSR)
(T4): This transition occurs after the device has been placed in the D3
STATE
Section 3.7.6, "Detecting Power Management Events," on page 80
HOT
A
state under the following conditions. State transitions are illustrated in
state under the following conditions. State transitions are illustrated in
Power Management State (PM_STATE)
Power Management State (PM_STATE)
Power Management State (PM_STATE)
DATASHEET
Power Management State (PM_STATE)
PME Enable (PME_EN)
HOT
77
to for more information on this reset.
(PCI_PMCSR). (PCInRST=1, PM_STATE=00b to 11b,
is cleared, the internal PHY is reset and is placed in
PME Enable (PME_EN)
will indicate a setting of 11b (D3 state).
is set to “D0”, and then PCI power is
(PCInRST=1, PM_STATE=11b to 00b,
bit in the
for more information.
field of the
field of the
field of the
HOT
PCI Power Management
state and Host system
field of the
is set, it is assumed
Revision 1.4 (12-17-08)
PCI Power
PCI Power
PCI Power
A
PME Enable
state
PCI Power
is cleared,
HOT
for more
state