LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 47

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
BITS
BITS
6:3
31
30
29
8
7
2
1
0
Transmit Descriptor 1 (TDES1)
EC - Excessive Collision
When set, indicates that the transmission was aborted after 16 successive collisions while
attempting to transmit the current frame.
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
RESERVED
Host Actions: Cleared on writes and ignored on reads.
DMAC Actions: Ignored on reads and cleared on writes.
CC - Collision Count
This 4-bit counter indicates the number of collisions that occurred before the frame was transmitted.
Not valid when the excessive collisions bit (EC - TDES0[8]) is also set.
Host Actions: Reads this field to determine Collision Count.
DMAC Actions: Initializes this field to define Collision Count.
ED - Excessive Deferral
If the deferred bit is set in the control register, the setting of the Excessive Deferral bit indicates
that the transmission has ended because of deferral of over 24,288-bit times during transmission.
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
Reserved
DE - Deferred
When set, indicates that the DMA Controller had to defer while ready to transmit a frame because
the carrier was asserted.
Host Actions: Checks this bit to determine status.
DMAC Actions: Sets/clears this bit to define status.
IC - Interrupt on Completion
When set, the DMA Controller sets transmit interrupt (TI - DMAC_STATUS[0]) after the present
frame has been transmitted. This field is valid only when last segment (LS - TDES1[30]) is set.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine whether IOC should be asserted.
LS - Last Segment
When set, indicates that the buffer contains the last segment of a frame.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine whether the buffer contains the last segment of a
frame.
FS - First Segment
When set, indicates that the buffer contains the first segment of a frame.
Host Actions: Initializes this bit.
DMAC Actions: Reads this bit to determine whether the buffer contains the first segment of a
frame.
Table 3.9 TDES0 Bit Fields (continued)
Table 3.10 TDES1 Bit Fields
DATASHEET
47
DESCRIPTION
DESCRIPTION
Revision 1.4 (12-17-08)