LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 29

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
.
SMSC LAN9420/LAN9420i
Wake Event Interrupt
GP Timer Interrupt
Master Bus Error
Slave Bus Error
GPIO2 Interrupt
GPIO0 Interrupt
GPIO1 Interrupt
DMAC Interrupt
Interrupt
Interrupt
PHY Interrupt
A Block diagram of the Interrupt Controller is shown in
The Interrupt Controller control and status register are contained within the System Control and Status
Registers (SCSR) block. The interrupt status register (INT_STS) reflects the current state of the
interrupt sources prior to qualification with their associated enables. The SW_INT, MBERR_INT,
SBERR_INT, GPIOx_INT, and GPT_INT are latched, and are cleared through the SCSR block upon a
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
(INT_CTL Register)
MBERR_INT_EN
SBERR_INT_EN
GPIO2_INT_EN
GPIO1_INT_EN
GPIO0_INT_EN
WAKE_INT_EN
General-purpose timer interrupt (GPT_INT)
General purpose Input/Output interrupt (GPIOx_INT)
Software interrupt (SW_INT)
Master bus error interrupt (MBERR_INT)
Slave bus error interrupt (SBERR_INT)
Wake event detection (WAKE_INT)
SW_INT_EN
GPT_INT_EN
PHY_INT_EN
RW
RW
RW
RW
RW
RW
RW
RW
RW
(INT_STS Register)
(INT_STS Register)
(INT_STS Register)
(INT_STS Register)
(INT_STS Register)
(INT_STS Register)
MBERR_INT
SBERR_INT
GPIO2_INT
GPIO1_INT
GPIO0_INT
GPT_INT
Figure 3.6 Interrupt Controller Block Diagram
RO
RO
RO
(INT_STS Register)
(INT_STS Register)
(INT_STS Register)
DETECT
DMAC_INT
WAKE_INT
0 to 1
PHY_INT
(INT_STS Register)
SW_INT
DATASHEET
Interrupt Controller
29
(INT_CFG Register)
(INT_CFG Register)
INT_DEAS_CLR
INT_DEAS[7:0]
Figure 3.6
RW
RW
(INT_CTL Register)
DEASSERTION
TIMER
IRQ_EN
(INT_CFG Register)
IRQ_INT
RO
RW
RO
(INT_CFG Register)
INT_DEAS_STS
Revision 1.4 (12-17-08)
(PCIB)
IRQ