CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 61

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
UART Control Register [0xC0E0] [R/W]
Register Description
The UART Control register enables or disables the UART
allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be
freed up for general use. This register must also be written to
set the baud rate, which is based on a 48-MHz clock.
Scale Select (Bit 4)
The Scale Select bit acts as a prescaler that will divide the
baud rate by eight.
1: Enable prescaler
0: Disable prescaler
UART Status Register [0xC0E2] [R]
Register Description
The UART Status register is a read-only register that indicates the status of the UART buffer.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
7
0
15
15
-
0
7
0
0
-
-
-
...Reserved
6
0
-
14
14
0
6
0
0
-
-
-
Figure 73. UART Control Register
Figure 74. UART Status Register
5
0
-
13
13
0
5
0
0
-
-
-
...Reserved
Select
4
0
Scale
-
R/W
12
12
4
0
0
0
-
-
Reserved...
Reserved...
Baud Select (Bits [3:1])
Refer to
Table 37.UART Baud Select Definition
UART Enable (Bit 0)
The UART Enable bit enables or disables the UART.
1: Enable UART
0: Disable UART. This allows GPIO6 and GPIO7 to be used
for general use
Reserved
All reserved bits must be written as ‘0’.
Baud Select [3:1]
3
0
Table 37
000
001
010
100
101
011
110
111
-
R/W
11
11
3
0
0
0
-
-
for a definition of this field.
2
0
-
Select
Baud
R/W
115.2K baud
10
10
2
1
57.6K baud
38.4K baud
28.8K baud
19.2K baud
14.4K baud
0
0
Baud Rate
w/DIV8 = 0
-
-
9.6K baud
7.2K baud
Receive Full
R
1
0
R/W
1
1
9
0
9
0
-
-
CY7C67200
14.4K baud
Baud Rate
w/DIV8 = 1
1.2K baud
0.9K baud
7.2K baud
4.8K baud
3.6K baud
2.4K baud
1.8K baud
Transmit Full
Page 61 of 78
Enable
UART
R
0
0
R/W
0
1
8
0
8
0
-
-
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