CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 52

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
HPI Status Port [] [HPI: R]
Register Description
The HPI Status Port provides the external host processor with
the MailBox status bits plus several SIE status bits. This
register is not accessible from the on-chip CPU. The additional
SIE status bits are provided to aid external device driver
firmware development, and are not recommended for applica-
tions that do not have an intimate relationship with the on-chip
BIOS.
Reading from the HPI Status Port does not result in a CPU HPI
interface memory access cycle. The external host may contin-
uously poll this register without degrading the CPU or DMA
performance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read-only bit that indicates whether
OTG VBus is greater than 4.4V. After turning on VBUS,
firmware should wait at least 10 µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
ID Flag (Bit 14)
The ID Flag bit is a read-only bit that indicates the state of the
OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read-only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read-only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read-only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Resume2
VBUS
Flag
Flag
15
R
X
R
X
7
Resume1
Flag
Flag
14
ID
R
X
R
X
6
Reserved
SIE2msg
13
X
R
X
5
-
Figure 60. HPI Status Port
SOF/EOP2
SIE1msg
Flag
12
R
R
X
X
4
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read-only bit that indicates if a
message is ready in the incoming mailbox. This interrupt
clears when on-chip CPU reads from the HPI Mailbox register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read-only bit that indicates if a USB
resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read-only bit that indicates if a USB
resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read-only bit that indicates if the
CY7C67200 CPU has written to the SIE2msg register. This bit
is cleared on an HPI read.
1: The SIE2msg register has been written by the CY7C67200
CPU
0: The SIE2msg register has not been written by the
CY7C67200 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read-only bit that indicates if the
CY7C67200 CPU has written to the SIE1msg register. This bit
is cleared on an HPI read.
1: The SIE1msg register has been written by the CY7C67200
CPU
0: The SIE1msg register has not been written by the
CY7C67200 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read-only bit that indicates
if a host packet done interrupt occurs on Host 2. In device
Reserved
Done2
Flag
11
R
X
X
3
-
SOF/EOP1
Done1
Flag
Flag
10
R
R
X
X
2
Reset2
Reset1
Flag
Flag
R
R
X
9
X
1
CY7C67200
Page 52 of 78
Mailbox Out
Mailbox In
Flag
Flag
R
X
R
X
0
8
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