CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 16

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
USB Diagnostic Register [0xC03C] [R/W]
Register Description
The USB Diagnostic Register provides control of diagnostic
modes. It is intended for use by device characterization tests,
not for normal operations. This register is Read/Write by the
on-chip CPU but is write-only via the HPI port.
Port 2A Diagnostic Enable (Bit 15)
The Port 2A Diagnostic Enable bit enables or disables Port 2A
for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K,
DCK, SE0, RSF, RSL, PRD
0: Do not apply test conditions
Port 1A Diagnostic Enable (Bit 15)
The Port 1A Diagnostic Enable bit enables or disables Port 1A
for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K,
DCK, SE0, RSF, RSL, PRD
0: Do not apply test conditions
Pull-down Enable (Bit 6)
The Pull-down Enable bit enables or disables full-speed
pull-down resistors (pull down on both D+ and D–) for testing.
1: Enable pull-down resistors on both D+ and D–
0: Disable pull-down resistors on both D+ and D–
LS Pull-up Enable (Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed
pull-up resistor (pull up on D–) for testing.
1: Enable low-speed pull-up resistor on D–
0: Pull-up resistor is not connected on D–
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
...Reserved
Reserved
15
0
7
0
-
-
Diagnostic
Pull-down
Port 2A
Enable
Enable
R/W
R/W
14
0
6
0
Figure 14. USB Diagnostic Register
LS Pull-up
Reserved
Enable
R/W
13
0
5
0
-
Diagnostic
FS Pull-up
Port 1A
Enable
Enable
R/W
R/W
12
0
4
0
FS Pull-up Enable (Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed
pull-up resistor (pull up on D+) for testing.
1: Enable full-speed pull-up resistor on D+
0: Pull-up resistor is not connected on D+
Force Select (Bits [2:0])
The Force Select field bit selects several different test
condition states on the data lines (D+/D–). See
details.
Table 19.Force Select Definition
Reserved
All reserved bits must be written as ‘0’.
Timer Registers
There are three registers dedicated to timer operations. Each
of these registers are discussed in this section and are
summarized in
Table 20.Timer Registers
Watchdog Timer Register
Timer 0 Register
Timer 1 Register
Force Select [2:0]
Register Name
Reserved
11
0
3
0
-
-
001
000
1xx
01x
Table
20.
R/W
10
0
2
0
-
Reserved...
Address
0xC00C
0xC010
0xC012
Force Select
Data Line State
R/W
9
0
1
0
-
Assert SE0
Toggle JK
CY7C67200
Assert K
Assert J
Page 16 of 78
Table 19
R/W
R/W
R/W
R/W
R/W
8
0
0
0
-
for
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