CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 11

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Bank Register [0xC002] [R/W]
Register Description
The Bank register maps registers R0–R15 into RAM. The
eleven MSBs of this register are used as a base address for
registers R0–R15. A register address is automatically
generated by:
For example, if the Bank register is left at its default value of
0x0100, and R2 is read, then the physical address 0x0102 will
be read. See
Hardware Revision Register [0xC004] [R]
Register Description
The Hardware Revision register is a read-only register that
indicates the silicon revision number. The first silicon revision
is represented by 0x0101. This number is increased by one for
each new silicon revision.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
1. Shifting the four LSBs of the register address left by 1
2. ORing the four shifted bits of the register address with the
3. Forcing the LSB to zero
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
12 MSBs of the Bank Register
Table 17
R/W
R/W
R
X
7
15
15
R
X
0
7
0
for details.
...Address
R/W
R/W
R
X
6
14
14
R
X
0
6
0
R/W
R/W
R
X
5
13
13
R
X
0
5
0
Figure 9. Revision Register
Figure 8. Bank Register
R/W
R
X
4
12
12
R
0
4
X
X
-
...Revision
.
Table 17.Bank Register Example
Address (Bits [15:4])
The Address field is used as a base address for all register
addresses to start from.
Reserved
All reserved bits must be written as ‘0’.
Revision...
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
Address...
Bank
R14
RAM
Location
Register
R/W
R
X
3
11
11
R
0
3
X
X
-
0x000E << 1 = 0x001C
Hex Value
0x011C
0x0100
Reserved
R/W
R
X
2
10
10
X
R
X
0
2
-
0000 0001 0000 0000
R/W
0000 0000 0001 1100
0000 0001 0001 1100
R
X
1
X
R
X
9
0
1
9
-
CY7C67200
Binary Value
Page 11 of 78
R/W
R
X
0
X
R
X
8
1
0
8
-
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