CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 36

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Device n Address Register [W]
Register Description
The Device n Address register holds the device address assigned by the host. This register initializes to the default address 0 at
reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained in
this register will be responded to, all others are ignored.
Address (Bits [6:0])
The Address field contains the USB address of the device assigned by the host.
Reserved
All reserved bits must be written as ‘0’.
Device n Status Register [R/W]
Register Description
The Device n Status register provides status information for
device operation. Pending interrupts can be cleared by writing
a ‘1’ to the corresponding bit. This register can be accessed
by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG
VBUS interrupt (only for Port 1A). When enabled this interrupt
triggers on both the rising and falling edge of VBUS at 4.4V.
This bit is only available for Device 1 and is a reserved bit in
Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device 1 Address Register 0xC08E
• Device 2 Address Register 0xC0AE
• Device 1 Status Register 0xC090
• Device 2 Status Register 0xC0B0
EP7 Interrupt
Interrupt Flag
...Reserved
VBUS
Flag
R/W
R/W
15
15
X
0
7
0
7
-
-
X
EP6 Interrupt
ID Interrupt
Flag
R/W
14
W
Flag
R/W
X
0
6
0
6
-
14
X
Figure 36. Device n Address Register
EP5 Interrupt
Figure 37. Device n Status Register
Flag
R/W
13
W
X
0
5
0
13
5
-
X
-
EP4 Interrupt
Flag
R/W
12
W
12
0
4
0
X
4
X
-
-
Reserved...
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID
interrupt (only for Port 1A). When enabled this interrupt
triggers on both the rising and falling edge of the OTG ID pin.
This bit is only available for Device 1 and is a reserved bit in
Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP
received interrupt has triggered.
1: Interrupt triggered
0: Interrupt did not trigger
Reserved
EP3 Interrupt
Address
Flag
R/W
11
X
11
W
-
0
3
0
3
X
-
EP2 Interrupt
10
Flag
R/W
X
-
10
W
0
2
0
2
X
-
Interrupt Flag
EP1 Interrupt
SOF/EOP
R/W
Flag
R/W
X
9
W
9
0
1
0
1
X
-
CY7C67200
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Interrupt Flag
EP0 Interrupt
Reset
R/W
Flag
R/W
W
8
X
8
0
0
0
X
-
0
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