CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 60

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
SPI Receive Address Register [0xC0DC [R/W]
Register Description
The SPI Receive Address register is issued as the base address for the SPI Receive DMA.
Address (Bits [15:0])
The Address field sets the base address for the SPI receive DMA.
SPI Receive Count Register [0xC0DE] [R/W]
Register Description
The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer.
Count (Bits [10:0])
The Count field sets the count for the SPI receive DMA transfer.
Reserved
All reserved bits must be written as ‘0’.
UART Registers
There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in
Table
Table 36.UART Registers
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
UART Control Register
UART Status Register
UART Data Register
36.
R/W
R/W
R/W
Register Name
15
15
0
7
0
0
7
0
-
R/W
R/W
R/W
14
14
0
6
0
0
6
0
-
Figure 71. SPI Receive Address Register
Figure 72. SPI Receive Count Register
Reserved
R/W
R/W
R/W
13
13
0
5
0
0
5
0
-
R/W
R/W
R/W
12
12
0
4
0
0
4
0
-
Address...
...Address
...Count
Address
0xC0E0
0xC0E2
0xC0E4
R/W
R/W
R/W
11
11
0
3
0
0
3
0
-
R/W
R/W
R/W
R/W
10
10
0
2
0
0
2
0
Count...
R/W
R/W
R/W
R/W
9
0
1
0
9
0
1
0
CY7C67200
R/W
R/W
R/W
R
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R/W
R/W
R/W
R/W
8
0
0
0
8
0
0
0
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