LTC4278CDKD#PBF Linear Technology, LTC4278CDKD#PBF Datasheet - Page 36

• Manufacturer Part Number: LTC4278CDKD#PBF
• Description: IC PD IEEE 802.3AT 25.5W 32-DFN
• Manufacturer: Linear Technology

Specifications of LTC4278CDKD#PBF

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 4.5 V ~ 20 V
• Current - Supply: 6.4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Input Voltage: 60V
• Supply Current: 1.35mA
• Digital Ic Case Style: DFN
• No. Of Pins: 32
• Duty Cycle (%): 88%
• Frequency: 100kHz
• Operating Temperature Range: °C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC4278
Capacitor Selection
In a fl yback converter, the input and output current fl ows
in pulses, placing severe demands on the input and output
fi lter capacitors. The input and output fi lter capacitors
are selected based on RMS current ratings and ripple
voltage.
Select an input capacitor with a ripple current rating
greater than:
Continuing the example:
Keep input capacitor series resistance (ESR) and inductance
(ESL) small, as they affect electromagnetic interference
suppression. In some instances, high ESR can also
produce stability problems because fl yback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater
than:
This is calculated for each output in a multiple winding
application.
ESR and ESL along with bulk capacitance directly affect the
output voltage ripple. The waveforms for a typical fl yback
converter are illustrated in Figure 17.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
36
I
I
I
I
Continuing
RMS PRI
RMS PRI
RMS SEC
RMS SEC
(
(
(
(
)
)
)
)
=
=
=
=
29 5
V
I
5 3
the exa a mple:
OUT
IN MIN
41
.
P
.
(
IN
A
V
W
− 1
)
1 49 4
DC
−
49 4
1 49 4
DC
− 1
−
49 4
MAX
. %
DC
MAX
. %
DC
. %
MAX
. %
MAX
=
5 24
=
.
0 728
.
A
A
starting point for the capacitor values. For the purpose
of simplicity, we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
The other 1% is due to the bulk C component, so use:
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfi es the required bulk C.
Continuing our example, the output capacitor needs:
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
RIPPLE WAVEFORM
ESR
C
ESR
C
OUTPUT VOLTAGE
OUT
OUT
SECONDARY
Figure 17. Typical Flyback Converter Waveforms
COUT
COUT
≥
≥
CURRENT
CURRENT
PRIMARY
1% • 5 • 200kHz
1% •
≤
≤1% •
1
% •
V
5.3A
I
OUT
OUT
ΔV
V
5V • 1− 49.4%
COUT
I
OUT
•
PRI
f
OSC
ΔV
(
ESR
•
5.3A
(
I
= 600μF
1
OUT
−
DC
MAX
I
)
PRI
N
= 4mΩ
)
DUE TO ESL
RINGING
4278 F17
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