LTC4278CDKD#PBF Linear Technology, LTC4278CDKD#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC4278CDKD#PBF
• Description: IC PD IEEE 802.3AT 25.5W 32-DFN
• Manufacturer: Linear Technology

Specifications of LTC4278CDKD#PBF

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 4.5 V ~ 20 V
• Current - Supply: 6.4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Input Voltage: 60V
• Supply Current: 1.35mA
• Digital Ic Case Style: DFN
• No. Of Pins: 32
• Duty Cycle (%): 88%
• Frequency: 100kHz
• Operating Temperature Range: °C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN FUNCTIONS
LTC4278
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4278
operation and corrupt the signature resistance. If unused,
tie SHDN to V
T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low imped-
ance indicates the presence of a Type 2 PSE.
R
between R
current (see Table 2).
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
V
Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchro-
nous rectifi er. Large dynamic currents may fl ow during
voltage transitions. See the Applications Information
section for details.
V
GND with a low ESR ceramic capacitor. See the Applica-
tions Information section for details.
t
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feed-
back method. See the Applications Information section
for details.
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifi er for a fi xed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for fl yback voltage sensing.
See the Applications Information section for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to
discharge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
10
ON
PORTN
CC
CLASS
(Pin 11): Pin for external programming resistor to
(Pin 10): Supply Voltage Pin. Bypass this pin to
(Pins 5, 6): Input Voltage, Negative Rail. Pin 5 and
(Pin 3): Class Select Input. Connect a resistor
CLASS
PORTN
and V
.
PORTN
to set the classifi cation load
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (C
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
the V
start is complete. The ramp time is approximately 70ms
per μF of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin, in conjunction with an
external capacitor (C
oscillator frequency. The frequency is approximately
100kHz • 100/C
FB (Pin 16): Feedback Amplifi er Input. Feedback is usually
sensed via a third winding and enabled during the fl yback
period. This pin also sinks additional current to compensate
for load current variation as set by the R
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
V
is used for frequency compensation of the switcher con-
trol loop. It is the output of the feedback amplifi er and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifi er output is enabled
during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
from V
upon V
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from V
The bias current on this pin has hysteresis such that the
bias current is sourced when UVLO threshold is exceeded.
This introduces a hysteresis at the pin equivalent to the bias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
pin to V
CMP
CMP
(Pin 17): Frequency Compensation Control. V
PORTP
PORTP
CC
voltage and thus limits peak current until soft-
if not using this function. See the Applications
SFST
to this pin sets an undervoltage lockout based
level (not V
OSC
) to GND, controls the ramp-up of peak
(pF).
OSC
CC
) to GND, defi nes the controller
). When the UVLO pin is below
CMP
CC
pin. Keep the
.
4278fa
CMP