LTC4278CDKD#PBF Linear Technology, LTC4278CDKD#PBF Datasheet - Page 20

• Manufacturer Part Number: LTC4278CDKD#PBF
• Description: IC PD IEEE 802.3AT 25.5W 32-DFN
• Manufacturer: Linear Technology

Specifications of LTC4278CDKD#PBF

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 4.5 V ~ 20 V
• Current - Supply: 6.4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Input Voltage: 60V
• Supply Current: 1.35mA
• Digital Ic Case Style: DFN
• No. Of Pins: 32
• Duty Cycle (%): 88%
• Frequency: 100kHz
• Operating Temperature Range: °C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC4278
Classifi cation Resistor (R
The R
corresponding to the PD power classifi cation. Select the
value of R
between the R
4, or fl oat the R
rent is not required. The resistor tolerance must be 1%
or better to avoid degrading the overall accuracy of the
classifi cation circuit.
Load Capacitor
The IEEE 802.3af/at specifi cation requires that the PD
maintains a minimum load capacitance of 5μF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store signifi cant energy when fully
charged. The PD design must ensure that this energy is
not inadvertently dissipated in the LTC4278. For example,
if the V
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4278.
T2P Interface
When a 2-event classifi cation sequence successfully
completes, the LTC4278 recognizes this sequence, and
provides an indicator bit, declaring the presence of a
Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4278 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an opto-isolator to communicate across the
20
CLASS
PORTP
CLASS
resistor sets the classifi cation load current,
CLASS
pin shorts to V
CLASS
from Table 2 and connect the resistor
and V
pin if the classifi cation load cur-
PORTN
CLASS
PORTN
)
pins as shown in Figure
while the capacitor
DC/DC converter isolation barrier. The pull-up resistor R
is sized according to the requirements of the opto-isolator
operating current, the pull-down capability of the T2P pin,
and the choice of V
PoE supply rail (which the LTC4278 V
from the voltage source that supplies power to the DC/DC
converter. Option 1 has the advantage of not drawing power
unless T2P is declared active.
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to V
SHDN directly to V
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
Auxiliary power can be injected into an LTC4278-based
PD at the input of the LTC4278 V
the power supply output. In addition, some PD applications
may desire auxiliary supply dominance or may be confi gured
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
PSE
PSE
TO
TO
–54V
–54V
Figure 8. T2P Interface Examples
V
V
PORTN
PORTN
PORTN
LTC4278
LTC4278
+
. V
V
V
+
PORTP
PORTP
V
.
for example can come from the
T2P
T2P
NEG
PORTN
PORTN
V
V
+
+
R
R
. If unused, connect
P
P
PORTP
, at V
is tied to), or
TO PD LOAD
TO PD LOAD
NEG
, or even
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