LTC4278CDKD#PBF Linear Technology, LTC4278CDKD#PBF Datasheet - Page 31

• Manufacturer Part Number: LTC4278CDKD#PBF
• Description: IC PD IEEE 802.3AT 25.5W 32-DFN
• Manufacturer: Linear Technology

Specifications of LTC4278CDKD#PBF

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 4.5 V ~ 20 V
• Current - Supply: 6.4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Input Voltage: 60V
• Supply Current: 1.35mA
• Digital Ic Case Style: DFN
• No. Of Pins: 32
• Duty Cycle (%): 88%
• Frequency: 100kHz
• Operating Temperature Range: °C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
between the primary-side switch and secondary-side syn-
chronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator effi ciency.
The primary gate delay resistor is set with the following
equation:
A good starting point is 15k.
Soft-Start Function
The LTC4278 contains an optional soft-start function that
is enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when the current sense voltage is greater
than 200mV or the IC’s thermal (overtemperature) shut-
down is tripped. When SFST discharges, the V
voltage is also pulled low to below the minimum current
voltage. Once discharged and the fault removed, the
SFST charges up again. In this manner, switch currents
are reduced and the stresses in the converter are reduced
during fault conditions.
The time it takes to fully charge soft-start is:
R
t
ss
PGDLY
=
C
SFST
( )
kΩ
20μA
• 1.4V
CMP
=
t
PGDLY
pin from exceeding that on the SFST
= 70kΩ • C
9.01
( )
ns
+ 47
SFST
( )
μF
CMP
node
Switcher’s UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on V
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at V
equal to the change in bias current times R
procedure is to select the desired V
hysteresis, V
where:
R
V
(13a) UV Turning On
IN
B
R
R
I
R
R
Figure 13. UVLO Pin Function and Recommended Filtering
A
B
UVLO
is then selected with the desired turn-on voltage:
B
A
=
UVLO
=
LTC4278
= I
V
V
I
V
UVHYS
UVLO
IN(ON)
UVLO
UVLOL
I
UVLO
UVHYS
R
A
– 1
– I
. Then:
IN
V
(13b) UV Turning Off
UVLOH
IN
. The gate drivers are disabled when
R
R
A
B
UVLO
is approximately 3.4μA
LTC4278
I
UVLO
IN
LTC4278
referred voltage
(13c) UV Filtering
A
C
. The design
UVLO
V
31
IN
R
R
R
4278 F13
A1
A2
B
IN
4278fa
UVLO
is