LTC4278CDKD#PBF Linear Technology, LTC4278CDKD#PBF Datasheet - Page 35

• Manufacturer Part Number: LTC4278CDKD#PBF
• Description: IC PD IEEE 802.3AT 25.5W 32-DFN
• Manufacturer: Linear Technology

Specifications of LTC4278CDKD#PBF

• Controller Type: Powered Device Interface Controller (PD)
• Interface: IEEE 802.3af
• Voltage - Supply: 4.5 V ~ 20 V
• Current - Supply: 6.4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Input Voltage: 60V
• Supply Current: 1.35mA
• Digital Ic Case Style: DFN
• No. Of Pins: 32
• Duty Cycle (%): 88%
• Frequency: 100kHz
• Operating Temperature Range: °C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
C
on most MOSFET data sheets (Figure 16).
The fl at portion of the curve is the result of the Miller (gate
to-drain) capacitance as the drain voltage drops. The Miller
capacitance is computed as:
The curve is done for a given V
for different V
computed C
the curve specifi ed V
With C
MOSFET power dissipation:
where:
(1 + δ) is generally given for a MOSFET in the form of a
normalized R
have a curve, use δ = 0.005/°C • ΔT for low voltage
MOSFETs.
MILLER
R
V
f
V
C
P
V
OSC
TH
D PRI
GATE(MAX)
DR
MILLER
IN MAX
(
(
MILLER
is the MOSFET gate threshold voltage
is the gate driver resistance (≈10Ω)
is the operating frequency
is calculated from the gate charge curve included
)
=
)
=
I
•
MILLER
RMS PRI
determined, calculate the primary-side power
P
DS
DS(ON)
Q
DC
= 7.5V for this part
I
N N MAX
V
Figure 16. Gate Charge Curve
B
GS
V
(
voltages are estimated by multiplying the
(
−
MIN
DS
Q
by the ratio of the application V
)
Q
vs temperature curve. If you don’t
A
2
a
)
DS
A
GATE CHARGE (Q
•
•
MILLER EFFECT
.
R
R
DR
DS ON
(
•
V
DS
)
GATE MAX
(
G
Q
1 δ
. The Miller capacitance
b
)
B
+
C
(
MILLER
)
4278 F16
+
)
−
V
TH
•
f
OSC
DS
to
The secondary-side power MOSFETs typically operate
at substantially lower V
losses. The dissipation is calculated using:
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
where T
junction to ambient thermal resistance.
Once you have T
δ and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves effi ciency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer effi ciency.
The LTC4278 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum V
Synchronous Gate Drive
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchro-
nous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
However, other schemes are possible. There are gate drivers
and secondary-side synchronous controllers available
that provide the buffer function as well as additional
features.
P
T
J
DIS(SEC)
= T
A
A
is the ambient temperature and θ
+ P
GS
= I
DIS
RMS(SEC)
of 10V and larger.
J
• θ
iterate your calculations recomputing
JA
DS
2
• R
, so you can neglect transition
DS(ON)
(1 + δ)
LTC4278
JA
is the MOSFET
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