UCB1400BE,151 NXP Semiconductors, UCB1400BE,151 Datasheet - Page 42

• Manufacturer Part Number: UCB1400BE,151
• Description: IC AUDIO CODEC 3.3V 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Codec '97r

Specifications of UCB1400BE,151

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 91
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935269304151; UCB1400BE-SNXP; UCB1400BE-SNXP

Philips Semiconductors
9397 750 09611
Product data
12.13 Positive INT Enable register (index 0x5E)
12.14 Negative INT Enable register (index 0x60)
Table 36:
Register address: 0x5E; default: 0000
Table 37:
Table 38:
Register address: 0x60; default: 0000
Table 39:
Bit
D15
D14
D13
D12
D11
D10
D9 - D0
Bit
D15
D14
D13
D12
D11
D10
D9 - D0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Positive INT Enable register
Description of Positive INT Enable register bits
Negative INT Enable register
Description of Negative INT Enable register bits
Symbol
OVLP
CLPP
TMXP
TPXP
ADCP
X
IOP9 - IOP0
Symbol
OVLN
CLPN
TMXN
TPXN
ADCN
X
ION9 - ION0
OVLP
OVLN
IOP7
ION7
D15
D15
D7
D7
Rev. 02 — 21 June 2002
CLPN
CLPP
IOP6
ION6
D14
D14
D6
D6
Type
RW
RW
RW
RW
RW
R
RW
Type
RW
RW
RW
RW
RW
R
RW
TMXN
TMXP
ION5
IOP5
D13
D13
D5
D5
Description
If ‘1’, the rising edge interrupt of the OVFL signal is
enabled.
If ‘1’, the rising edge interrupt of the CLIP signal is
enabled.
If ‘1’, the rising edge interrupt of the TSMX signal is
enabled.
If ‘1’, the rising edge interrupt of the TSPX signal is
enabled.
If ‘1’, the rising edge interrupt of ADC Ready is enabled.
Reserved.
If a bit is ‘1’, the rising edge interrupt of the associated
IO pin is enabled.
Description
If ‘1’, the falling edge interrupt of the OVFL signal is
enabled.
If ‘1’, the falling edge interrupt of the CLIP signal is
enabled.
If ‘1’, the falling edge interrupt of the TSMX signal is
enabled.
If ‘1’, the falling edge interrupt of the TSPX signal is
enabled.
If ‘1’, the falling edge interrupt of ADC Ready is enabled.
Reserved.
If a bit is ‘1’, the falling edge interrupt of the associated
IO pin is enabled.
TPXP
TPXN
ION4
IOP4
Audio codec with touch screen controller
D12
D12
D4
D4
ADCP
ADCN
IOP3
ION3
and power management monitor
D11
D11
D3
D3
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ION2
IOP2
D10
D10
D2
D2
X
X
UCB1400
ION9
ION1
IOP9
IOP1
D9
D1
D9
D1
IOP8
IOP0
ION8
ION0
42 of 63
D8
D0
D8
D0