UCB1400BE,151 NXP Semiconductors, UCB1400BE,151 Datasheet - Page 11

• Manufacturer Part Number: UCB1400BE,151
• Description: IC AUDIO CODEC 3.3V 48-LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Codec '97r

Specifications of UCB1400BE,151

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 91
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935269304151; UCB1400BE-SNXP; UCB1400BE-SNXP

Philips Semiconductors
9397 750 09611
Product data
Fig 8. AC-link audio input frame.
END OF PREVIOUS
SDATA_IN
BIT_CLK
AUDIO FRAME
SYNC
CODEC
READY
slot(1)
(“1” = TIME SLOT CONTAINS VALID PCM DATA)
TAG PHASE
slot(2)
81.4 ns
(12.288 MHz)
A new audio input frame begins with a LOW-to-HIGH transition of SYNC. SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, UCB1400 samples the assertion of SYNC. This falling edge marks the
time when both sides of AC-link are aware of the start of a new audio frame. On the
next rising edge of BIT_CLK, UCB1400 transitions SDATA_IN into the first bit position
of slot 0 (‘Codec Ready’ bit). Each new bit position is presented to AC-link on a rising
edge of BIT_CLK, and subsequently sampled by the AC ’97 Controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time
aligned.
SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit
positions (for assigned and/or unassigned time slots) stuffed with 0s by the UCB1400.
SDATA_IN data is sampled on the falling edges of BIT_CLK.
Fig 9. Start of an audio input frame.
TIME SLOT “VALID” BITS
slot(12)
“0”
SDATA_IN
“0”
BIT_CLK
Rev. 02 — 21 June 2002
SYNC
“0”
END OF PREVIOUS
(48 kHz)
20.8 s
19
AUDIO FRAME
SLOT 1
0
19
CODEC
READY
AC ’97 SAMPLES SYNC ASSERTION HERE
Audio codec with touch screen controller
SLOT 2
DATA PHASE
AC ’97 CONTROLLER SAMPLES FIRST
SDATA_IN BIT OF FRAME HERE
0
slot(1)
and power management monitor
19
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
SLOT 3
slot(2)
0
SN00224
UCB1400
19
SLOT 12
SN00223
0
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