IDTSTAC9752XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9752XXTAEB2XR Datasheet - Page 84

• Manufacturer Part Number: IDTSTAC9752XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9752XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9752XXTAEB2XR

11. TESTABILITY
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
11.0.1.
The STAC9752/9753 has two test modes. One is for ATE in-circuit test and the other is restricted for
manufacturer’s internal use. The STAC9752/9753 enters the ATE in-circuit test mode if
SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital
AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE
in-circuit testing of the AC'97 controller. Use of the ATE test mode is the recommended means of
removing the CODEC from the AC-Link when another CODEC is to be used as the primary. This
case will never occur during standard operating conditions. Once either of the two test modes have
been entered, the STAC9752/9753 must be issued another RESET# with all AC-Link signals held
low to return to the normal operating mode.
ATE Test Mode
ATE test mode allows for in-circuit testing to be completed at the board level. For this to work, the
outputs of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O
pins must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a
cold reset will exit the ATE Test Mode.
Note: Pins 31, 33, and 34 are NO CONNECTS.
SDATA_OUT
SDATA_IN
Pin Name
BIT_CLK
RESET#
SYNC
GPIO0
GPIO1
SPDIF
SYNC
EAPD
CID0
CID1
N.C.
N.C.
N.C.
0
0
1
1
SDATA_OUT
Pin #
10
11
31
33
34
43
44
45
46
47
48
5
6
8
0
1
0
1
Table 31. ATE Test Mode Operation
Table 30. Test Mode Activation
84
Function
1
Z
Z
0
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Must be held high at the rising edge of RESET#
Must be held low at rising edge of RESET#
Always an input
Always an input
Always an input
Normal AC'97 operation
IDT Internal Test Mode
STAC9752/9753
ATE Test Mode
Description
Reserved
Description
REV 3.3 1206