IDTSTAC9752XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9752XXTAEB2XR Datasheet - Page 16

• Manufacturer Part Number: IDTSTAC9752XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9752XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9752XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
2.2.
2.2.1.
2.2.2.
AC Timing Characteristics
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
RESET# active low pulse width
RESET# inactive to SDATA_IN or BIT_CLK active delay
RESET# inactive to BIT_CLK startup delay
BIT_CLK active to RESET# asserted (Not shown in diagram)
S D A T A _ I N
BIT_CLK
R E S E T #
(T
load for BIT_CLK and 60 pF external load for SDATA_IN)
Cold Reset
Warm Reset
Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.
ambient
BIT_CLK
= 25 °C, AVdd = 3.3 V or 5 V ± 5%, DVdd = 3.3 V ± 5%, AVss=DVss=0 V; 75 pF external
SYNC
Parameter
Parameter
Figure 3. Warm Reset Timing
Figure 2. Cold Reset Timing
16
T r e s _ l o w
Tsync_high
Tres_low
Symbol
Tri2actv
Trst2clk
Tclk2rst
Tsync_high
Tsync2clk
Symbol
Tsync_2clk
Ttri2actv
Ttri2actv
Trst2clk
STAC9752/9753
0.01628
0.416
Min
1.0
162.8
Min
-
1.0
Typ
Typ
1.3
-
-
-
-
-
Max
Max
400
25
-
-
-
-
REV 3.3 1206
Units
Units
ns
ns
s
s
s
s