IDTSTAC9752XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9752XXTAEB2XR Datasheet - Page 24

• Manufacturer Part Number: IDTSTAC9752XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9752XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9752XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
The STAC9752/9753 uses the XTAL_OUT Pin (Pin 3) and the CID0 and CID1 pins (Pins 45 & 46) to
determine its alternate clock frequencies. See section 2.2.4: page17 for additional information on
Crystal Elimination and for supported clock frequencies.
If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on
BIT_CLK as defined in the previous paragraph, then the AC‘97 CODEC derives its clock internally
from an externally attached 24.576 MHz crystal or oscillator, or optionally from an external
14.31 MHz oscillator, and drives a buffered 12.288 MHz clock to its digital companion Controller
over AC-Link under the signal name “BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental
impediment to high quality output, and the internally generated clock will provide AC‘97 with a clean
clock that is independent of the physical proximity of AC‘97’s companion Digital Controller (hence-
forth referred to as “the Controller”).
If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by
other than the primary CODEC, for instance by the controller or by a discrete clock source. In this
case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary
CODEC.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-Link is synchro-
nized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller gener-
RESET# Signal Asserted
Error condition - no clock
After RESET# Signal
AC'97 Clock Source
BIT_CLK Toggling?
oscillator presnent?
oscillator present?
crystal present?
source present
Deasserted
24.576MHz
24.576MHz
14.318MHz
Detection
Figure 12. CODEC Clock Source Detection
No
No
No
No
Yes
Yes
Yes
Yes
24
being generated externally; codec
12.288MHz signal on BIT_CLK is
and XTL_OUT used by codec to
24.576MHz Crystal on XTL_IN
24.576 MHz signal on XTL_IN
12.288MHz clock on BIT_CLK
14.318 MHz signal on XTL_IN
12.288MHz clock on BIT_CLK
uses this signal as the clock.
generate clock on BIT_CLK
used by codec to generate
used by codec to generate
STAC9752/9753
REV 3.3 1206