TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 43

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

13. Preparation for Delivery
13.1
13.2
13.3
13.4
5410B–HIREL–09/05
Packaging
Certificate of Compliance
Handling
Choice of Clock Relationships
A superscalar processor is one that issues multiple independent instructions into multiple pipe-
lines allowing instructions to execute in parallel. The 603R has five independent execution units,
one each for integer instructions, floating-point instructions, branch instructions, load/store
instructions, and system register instructions. The IU and the FPU each have dedicated register
files for maintaining operands (GPRs and FPRs, respectively), enabling integer calculations and
floating-point calculations to occur simultaneously without interference.
Because the PowerPC architecture can be applied to such a wide variety of implementations,
instruction timing among various PowerPC processors varies accordingly.
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in
compliance with the MIL-STD-883 standard and guaranteeing the parameters that are not tested
at temperature extremes for the entire temperature range.
MOS devices must be handled with certain precautions to avoid damage caused by an accumu-
lation of static charge. Input protection devices have been designed in the chip to minimize the
effect of this static buildup. However, the following handling practices are recommended:
The 603R microprocessors provide customers with numerous clocking options. An internal
phase-lock loop synchronizes the processor (CPU) clock to the bus or system clock (SYSCLK)
at various ratios.
Inside each PowerPC microprocessor is a phase-lock loop circuit. A Voltage Controlled Oscilla-
tor (VCO) is precisely controlled in frequency and phase by a frequency/phase detector which
compares the input bus frequency (SYSCLK frequency) to a submultiple of the VCO.
The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1
bus mode).
• The complete/writeback pipeline stage maintains the correct architectural machine state and
1. The devices should be handled on benches with conductive and grounded surfaces.
2. Ground test equipment and tools should be used.
3. The devices should not be handled by the leads.
4. The devices should be stored in conductive foam or carriers.
5. Use of plastic, rubber, or silk in MOS areas should be avoided.
6. Relative humidity above 50 percent should be maintained if practical.
transfers the contents of the rename registers to the GPRs and FPRs as instructions are
retired. If the completion logic detects an instruction causing an exception, all following
instructions are cancelled, their execution results in rename registers are discarded, and
instructions are fetched from the correct instruction stream.
TSPC603R
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