TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 20

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 10-5.
Table 10-6.
20
Signal Name
Address Bus
Data Bus
Data Bus
Signal Name
Address Acknowledge
Address Bus Busy
Address Bus Parity
Address Parity Error
Address Retry
Bus Grant
Bus Request
Cache Inhibit
Checkstop Input
Checkstop Output
Cache Set Entry
Data Bus Busy
Data Bus Disable
Data Bus Grant
Data Bus Write Only
Data Bus Parity
Data Parity Error
Data Retry
TSPC603R
Address and Data Bus Signal Index for Cerquad, CBGA 255 and CI-CGA 255 Packages
Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages
Abbreviation
AACK
ABB
AP[0-3]
APE
ARTRY
BG
BR
Cl
CKSTP_IN
CKSTP_OUT
CSE[0-1]
DBB
DBDIS
DBG
DBW0
DP[0-7]
DPE
DRTRY
Abbreviation
A[0-31]
DH[0-31]
DL[0-31]
Signal Function
The address phase of a transaction is complete
If output, the 603R is the address bus master
If input, the address bus is in use
If output, represents odd parity for each of 4 bytes of the physical address for a
transaction
If input, represents odd parity for each of 4 bytes of the physical address for
snooping operations
Incorrect address bus parity detected on a snoop
If output, detects a condition in which a snooped address tenure must be
retried
If input, must retry the preceding address tenure
May, with the proper qualification, assume mastership of the address bus
Request mastership of the address bus
A single-beat transfer will not be cached
Must terminate operation by internally gating off all clocks, and release all
outputs
Has detected a checkstop condition and has ceased operation
Cache replacement set element for the current transaction reloading into or
writing out of the cache
If output, the 603R is the data bus master
If input, another device is bus master
(For a write transaction) must release data bus and the data bus parity to high
impedance during the following cycle
May, with the proper qualification, assume mastership of the data bus
May run the data bus tenure
If output, odd parity for each of 8 bytes of data write transactions
If input, odd parity for each byte of read data
Incorrect data bus parity
Must invalidate the data from the previous read operation
Signal Function
If output, physical address of data to be transferred
If input, represents the physical address of a snoop operation
Represents the state of data, during a data write operation if output, or during a
data read operation if input
Represents the state of data, during a data write operation if output, or during a
data read operation if input
5410B–HIREL–09/05
Signal
Type
Input
I/O
I/O
Output
I/O
Input
Output
Output
Input
Output
Output
I/O
Input
Input
Input
I/O
Output
Input
Signal
Type
I/O
I/O
I/O