TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 30

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

12.1.7
30
TSPC603R
Special-purpose Registers (SPRs)
The powerPC operating environment architecture defines numerous special-purpose registers
that serve a variety of functions, such as providing controls, indicating status, configuring the
processor, and performing special operations. During normal execution, a program can access
the registers, shown in
(supervisor or user, determined by the privilege-level (PR) bit in the MSR. Note that registers
such as the GPRs and FPRs are accessed through operands that are part of the instructions.
Access to registers can be explicit (that is, through the use of specific instructions for that pur-
pose such as Move to special-purpose register (mtspr) and move from special-purpose register
(mfspr) instructions or implicit, as the part of the execution of an instruction. Some registers are
accessed both explicitly and implicitly.
In the 603R, all SPRs are 32 bits wide.
The 603R also contains SPRs that can be accessed only by supervisor-level software. These
registers consist of the following:
• User-level SPRs:
• Supervisor-level SPRs:
The following 603R SPRs are accessible by user-level software:
– Link Register (LR) - The link register can be used to provide the branch target
– Count Register (CTR) - The CRT is decremented and tested automatically as a
– Integer Exception Register (XER) - The 32-bit XER contains the summary overflow
– The 32-bit DSISR defines the cause of data access and alignment exceptions.
– The Data Address Register (DAR) is a 32-bit register that holds the address of an
– Decrementer register (DEC) is a 32-bit decrementing counter that provides a
– The 32-bit SDR1 specifies the page table format used in virtual-to-physical address
– The machine status Save/Restore Register 0 (SRR0) is a 32-bit register that is used
– The machine status Save/Restore Register 1 (SRR1) is a 32-bit register used to
– The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
– The External Access Register (EAR) is a 32-bit register that controls access to the
address and to hold the return address after branch and link instructions. The LR is
32 bits wide in 32-bit implementations.
result of branch-and-count instructions. The CTR is 32 bits wide in 32-bit
implementations.
bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be
transferred by a Load String Word Indexed (LSWX) or Store String Word Indexed
(STSWX) instruction.
access after an alignment or DSI exception.
mechanism for causing a decrementer exception after a programmable delay.
translation for pages. (Note that physical address is referred to as real address in the
architecture specification).
by the 603R for saving the address of the instruction that caused the exception, and
the address to return to when a Return from Interrupt (RFI) instruction is executed.
save machine status on exceptions and to restore machine status when an RFI
instruction is executed.
external control facility through the External Control In Word Indexed (ECIWX) and
External Control Out Word Indexed (ECOWX) instructions.
Figure 12-1 on page
32, depending on the program’s access privilege
5410B–HIREL–09/05