TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 11

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

5410B–HIREL–09/05
Doze Mode
The doze mode disables most functional units but maintains cache coherency by enabling the
bus interface unit and snooping. A snoop hit will cause the 603R to enable the data cache, copy
the data back to the memory, disable the cache, and fully return to the doze state. In this mode:
Nap Mode
The nap mode disables the 603R but still maintains the phase locked loop (PLL) and the time
base/decrementer. The time base can be used to restore the 603R to full-on state after a pro-
grammed amount of time. Because bus snooping is disabled for nap and sleep modes, a
hardware handshake using the quiesce request (QREQ) and quiesce acknowledge (QACK) sig-
nals is required to maintain data coherency. The 603R will assert the QREQ signal to indicate
that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it will assert QACK and the 603R will enter the sleep or nap mode. In this
mode:
• Functional units are clocked only when needed
• No software or hardware intervention required after mode is set
• Software/hardware and performance are transparent
• Most functional units are disabled
• Bus snooping and time base/decrementer are still enabled
• Dose mode sequence:
• There are several methods for returning to full-power mode
• The Transition to full-power state takes no more than a few processor cycles
• Phase Locked Loop (PLL) running and locked to SYSCLK
• The time base/decrementer is still enabled
• Most functional units are disabled (including bus snooping)
• All non-essential input receivers are disabled
• Nap mode sequence:
• There are several methods for returning to full-power mode:
• Transition to full-power takes no more than a few processor cycles
• The PLL is running and locked to SYSCLK
– Set doze bit (HID0[8) = 1)
– 603R enters doze mode after several processor clocks
– Assert INT, SMI, MCP or decrementer interrupts
– Assert hard reset or soft reset
– Set nap bit (HID0[9] = 1)
– 603R asserts quiesce request (QREQ) signal
– System asserts quiesce acknowledge (QACK) signal
– 603R enters sleep mode after several processor clocks
– Assert INT, SPI, MCP or decrementer interrupts
– Assert hard reset or soft reset
TSPC603R
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