PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 8

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8
PC7457
• Efficient data flow
• Multiprocessing support features include the following:
• Power and thermal management
– Memory programmable as write-back/write-through, caching-inhibited/caching-
– Separate IBATs and DBATs (eight each) also defined as SPRs
– Separate instruction and data translation lookaside buffers (TLBs)
– Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to
– The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs
– L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1
– As many as eight outstanding, out-of-order, cache misses are allowed between the
– As many as 16 out-of-order transactions can be present on the MPX bus
– Store merging for multiple store misses to the same line. Only coherency action
– Three-entry finished store queue and five-entry completed store queue between the
– Separate additional queues for efficient buffering of outbound data (such as castouts
– Hardware-enforced, MESI cache coherency protocols for data cache
– Load/store with reservation instruction pair for atomic memory references,
– 1.6V processor core
– The following three power-saving modes are available to the system:
allowed, and memory coherency enforced/memory coherency not enforced on a
page or block basis
Both TLBs are 128-entry, two-way set-associative, and use LRU replacement
algorithm
TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table
search is performed in hardware or by system software)
256 bits
cache
L1 data cache and L2/L3 bus
taken (address-only) for store misses merged to all 32 bytes of a cache block (no
data tenure needed)
LSU and the L1 data cache
and write-through stores) from the L1 data cache and L2 cache
semaphores, and other multiprocessor operations
Nap—Instruction fetching is halted. Only those clocks for the time base,
decrementer, and JTAG logic remain running. The part goes into the doze state to
snoop memory operations on the bus and then back to nap using a QREQ/QACK
processor-system handshake protocol
Sleep—Power consumption is further reduced by disabling bus snooping, leaving
only the PLL in a locked and running state. All internal functional units are disabled
Deep sleep—When the part is in the sleep state, the system can disable the PLL.
The system can then disable the SYSCLK source for greater system power savings.
Power-on reset procedures for restarting and relocking the PLL must be followed on
exiting the deep sleep state
5345D–HIREL–07/06