PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 50

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

15.1.3
15.2
50
PLL Power Supply Filtering
PC7457
System Bus Clock (SYSCLK) and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic inter-
ference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the
peak noise magnitude in order to meet industry and government requirements. These clock
sources intentionally add long-term jitter in order to diffuse the EMI spectral content. The jitter
specification given in
the clock generator’s cycle-to-cycle output jitter should meet the PC7457 input cycle-to-cycle jit-
ter requirement. Frequency modulation and spread are separate concerns, and the PC7457 is
compatible with spread spectrum sources if the recommendations listed in Table 20 are
observed.
Table 15-3.
Notes:
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO
frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in
which the processor is operated at its maximum rated core or bus frequency should avoid violat-
ing the stated limits by using down-spreading only.
The AV
To ensure stability of the internal clock, the power supplied to the AV
tered of any noise in the 500_kHz to 10 MHz resonant frequency range of the PLL. A circuit
similar to the one shown in
series inductance (ESL) is recommended.
The circuit should be placed as close as possible to the AV
nearby circuits. It is often possible to route directly from the capacitors to the AV
on the periphery of the 360 CBGA footprint and very close to the periphery of the 483 CBGA
footprint, without the inductance of vias.
Figure 15-1. PLL Power Supply Filter Circuit
Previous revisions of this document required a 400 . resistor for Rev. 1.1 (Rev. B) devices
instead of the 10 . resistor shown above. All production devices require a 10 . resistor. For
more information, see the PC7450 Family Chip Errata for the PC7457 and PC7447.
Parameter
Frequency modulation
Frequency spread
DD
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO fre-
power signal is provided on the PC7457 to provide power to the clock generation PLL.
quencies, must meet the minimum and maximum specifications given in
Spread Specturm Clock Source Recommendations (at Recommended Operating
Conditions, see
V DD
Table 7-2 on page 20
Figure 9-1
400Ω
page
Min
–
–
12.)
2.2 µF
using surface mount capacitors with minimum effective
considers short-term (cycle-to-cycle) jitter only and
GND
Low ESL surface mount capacitor
Max
1.0
50
2.2 µF
DD
pin to minimize noise coupled from
DD
Unit
kHz
%
AV DD
input signal should be fil-
Table 7-2 on page
DD
5345D–HIREL–07/06
pin, which is
Notes
(1)(2)
(1)
20.