PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 27

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.2.4.1
5345D–HIREL–07/06
Effects of L3OHCR Settings on L3 Bus AC Specifications
More specifically, certain signals within groups should be delay-matched with others in the same
group while intergroup routing is less critical. Only the address and control signals are common
to both SRAMs and additional timing margin is available for these signals. The double-clocked
data signals are grouped with individual clocks as shown in
on page
Figure
from the PC7457; while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0] form a closely cou-
pled group of inputs.
The PC7450 RISC Microprocessor Family User’s Manual refers to logical settings called "sam-
ple points" used in the synchronization of reads from the receive FIFO. The computation of the
correct value for this setting is system-dependent and is described in the PC7450 RISC Micro-
processor Family User’s Manual.
Three specifications are used in this calculation and are given in
essential that all three specifications are included in the calculations to determine the sample
points as incorrect settings can result in errors and unpredictable behavior. For more informa-
tion, see the PC7450 RISC Microprocessor Family User’s Manual.
Table 7-5.
Notes:
The AC timing of the L3 interface can be adjusted using the L3 Output Hold Control Register
(L3OCHR).
Each field controls the timing for a group of signals. The AC timing specifications presented
herein represent the AC timing when the register contains the default value of 0x0000_0000.
Incrementing a field delays the associated signals, increasing the output valid time and hold time
of the affected signals. In the special case of delaying an L3_CLK signal, the net effect is to
decrease the output valid and output hold times of all signals being latched relative to that clock
signal. The amount of delay added is summarized in
tings affect output timing parameters only and
in any way.
Symbol
t
t
t
AC
CO
ECI
7-6); L3DATA[0:31], L3DP[0:3], and L3_CLK[0] form a closely coupled group of outputs
1. This specification describes a logical offset between the internal clock edge used to launch the
2. This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the
3. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to data valid
32, depending on the type of SRAM. For example, for the MSUG2 DDR SRAM (see
L3 address and control signals (this clock edge is phase-aligned with the processor clock
edge) and the internal clock edge used to launch the L3_CLK[n] signals. With proper board
routing, this offset ensures that the L3_CLK[n] edge will arrive at the SRAM within a valid
address window and provide adequate setup and hold time. This offset is reflected in the L3
bus interface AC timing specifications, but must also be separately accounted for in the calcu-
lation of sample points and, thus, is specified here.
corresponding rising or falling edge at the L3CLK[n] pins.
and ready to be sampled from the FIFO.
Sample Points Calculation Parameters
Parameter
Delay from processor clock to internal_L3_CLK
Delay from internal_L3_CLK to L3_CLK[n] output pins
Delay from L3_ECHO_CLK[n] to receive latch
don’t
impact input timing parameters of the L3 bus
Table 7-6 on page
(3)
(1)
Figure 7-6 on page 30
(2)
Table 7-5 on page
28. Note that these set-
Max
3/4
3
3
PC7457
or
Figure 7-8
t
27. It is
L3_CLK
Unit
ns
ns
27