PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 25

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 7-4.
Notes:
5345D–HIREL–07/06
Symbol
f
t
t
t
t
L3_CLK
L3_CLK
CHCL
L3CSKW1
L3CSKW2
/t
L3_CLK
(1)
(1)
1. The maximum L3 clock frequency (and minimum L3 clock period) will be system dependent. See
2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals
4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or
5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data and
6. L3 I/O voltage mode must be configured by L3VSEL as described in
(3)
(4)
tions” on page 24
minimum L3 clock frequency and period are f
which are common to both SRAM chips in the L3.
Late Write SRAM. This parameter is critical to the read data signals because the processor uses the feedback loop to latch
data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.
control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the
L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period caused by supply voltage
noise or thermal effects. This is also comprehended in the AC timing specifications and need not be considered in the L3
timing analysis.
must match mode selected as specified in
(2)
L3_CLK Output AC Timing Specifications at Recommended Operating Conditions (see
Parameter
L3 clock frequency
L3 clock cycle time
L3 clock duty cycle
L3 clock output-to-output skew
(L3_CLK0 to L3_CLK1)
L3 clock output-to-output skew
(L3_CLK[0:1] to L3_ECHO_CLK[1:3])
L3 clock jitter
Note that SYSCLK input jitter and L3_CLK[0:1] output jitter are already comprehended in the L3
bus AC timing specifications and do not need to be separately accounted for in an L3 AC timing
analysis.
Clock skews, where applicable, do need to be accounted for in an AC timing analysis.Freescale
is similarly limited by system constraints and cannot perform tests of the L3 interface on a sock-
eted part on a functional tester at the maximum frequencies of
operation and AC timing information are tested at core-to-L3 divisors which result in L3 frequen-
cies at 250 MHz or lower.
for an explanation that this maximum frequency is not functionally tested at speed by Freescale. The
(5)
“Recommended Operating Conditions
SYSCLK
Min
–
–
–
–
–
–
and t
SYSCLK
Typical
200
50
5
–
–
–
, respectively.
Table 6-1 on page
All Speed Grades
Max
100
100
±75
–
–
(1)
” on page
Min
–
–
–
–
–
–
13, and voltage supplied at GV
Table
Typical
12.
250
50
7-4. Therefore, functional
4
–
–
–
“L3 Clock AC Specifica-
page
Max
±75
100
100
–
–
–
12)
PC7457
(6)
MHz
Unit
ns
ps
ps
ps
%
DD
25