PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 22

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

7.2.2
Table 7-3.
Notes:
22
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVKH
DVKH
IVKH
MVKH
AXKH
DXKH
IXKH
MXKH
KHAV
KHDV
KHOV
KHAX
KHDX
KHOX
KHOE
KHOZ
KHTSPZ
KHARP
KHARPZ
(8)
(8)
(3)(5)(6)(7)
(3)(4)(5)
(3)(5)(6)(7)
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
(2)
PC7457
Processor Bus AC Specifications
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-
nal in question. All output timings assume a purely resistive 50 load (see
are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
Processor Bus AC Timing Specifications
Parameter
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1],
BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN, SHD[0:1]
BMODE[0:1], BMODE[0:1], BVSEL, L3VSEL
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
SYSCLK to output enable
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
SYSCLK to TS high impedance after precharge
Maximum delay to ARTRY/SHD0/SHD1 precharge
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
Table 7-3
ure 7-10 on page 33
provided in section
provides the processor bus AC timing specifications for the PC7457 as defined in
“L3 Clock AC Specifications” on page
and
Figure 7-2 on page
(1)
(at Recommended Operating Conditions, see
V
23. Timing specifications for the L3 bus are
DD
Figure 7-10 on page
2.0
2.0
2.0
0.5
0.5
0.5
0.5
= 1.1V
2
0
0
0
0
–
–
–
–
–
–
–
24.
All Speed Grades
V
DD
Min
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
= 1.3V
–
–
0
0
0
0
–
–
–
–
–
33). Input and output timings
page
Max
3.5
–
–
–
–
–
–
–
–
2
2
2
–
–
–
–
1
1
2
5345D–HIREL–07/06
12.)
t
t
t
SYSCLK
SYSCLK
SYSCLK
Unit
ns
ns
ns
ns
ns
ns
Fig-