PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 26

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 7-4.
7.2.4
26
PC7457
For PB2 or Late Write:
L3 Bus AC Specifications
L3_CLK_OUT Output Timing Diagram
L3_ECHO_CLK1
L3_ECHO_CLK3
L3_CLK0
L3_CLK1
The PC7457 L3 interface supports three different types of SRAM: source-synchronous, double
data rate (DDR) MSUG2 SRAM, Late Write SRAMs, and pipeline burst (PB2) SRAMs. Each
requires a different protocol on the L3 interface and a different routing of the L3 clock signals.
The type of SRAM is programmed in L3CR[22:23] and the PC7457 then follows the appropriate
protocol for that type. The designer must connect and route the L3 signals appropriately for each
type of SRAM. Following are some observations about the L3 interface.
Figure 7-5.
In general, if routing is short, delay-matched, and designed for incident wave reception and min-
imal reflection, there is a high probability that the AC timing of the PC7457 L3 interface will meet
the maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimis-
tic, guard-banded AC specifications (see
Table 7-8 on page
Specifications” on page 24
worst-case critical path timing analysis pessimistic.
• The routing for the point-to-point signals (L3_CLK[0:1], L3DATA[0:63], L3DP[0:7], and
• For 1M byte of SRAM, use L3_ADDR[16:0] (L3_ADDR[0] is LSB)
• For 2M bytes of SRAM, use L3_ADDR[17:0] (L3_ADDR[0] is LSB)
• No pull-up resistors are required for the L3 interface
• For high speed operations, L3 interface address and control signals should be a "T" with
L3_ECHO_CLK[0:3]) to a particular SRAM must be delay matched
minimal stubs to the two loads; data and clock signals should be point-to-point to their single
load.
Figure 7-5
AC Test Load for the L3 Interface
VM
VM
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t CHCL
Output
shows the AC test load for the L3 interface
31), the limitations of functional testers described in Section
t L3_CLK
VM
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VM
and the uncertainty of clocks and signals which inevitably make
Z 0 = 50Ω
VM
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Table 7-6 on page
t L3CR
R L = 50Ω
VM
VM
28,
VM
t L3CSKW2
t L3CSKW2
t L3CSKW1
Table 7-7 on page
OV DD / 2
t L3CF
5345D–HIREL–07/06
“L3 Clock AC
29, and