PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 23

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

5345D–HIREL–07/06
2. The symbology used for timing specifications herein follows the pattern of t
3. t
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Tim-
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters
t
the SYSCLK reference (K) going to the high (H) state or input setup time. And t
going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal
(I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and
output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
before returning to high impedance as shown in
that is, less than the minimum t
tend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge.The high-impedance behavior is guaranteed by design.
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK will then go to high impedance for one clock before precharging it high during the second
cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t
ance as shown in
output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
ing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is
1.0 t
represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These
inputs must remain stable after the second sample. See
(reference)(state)(signal)(state)
SYSCLK
SYSCLK
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
Figure 7-2.
Figure 7-3 on page 24
Mode Signals
for outputs. For example, t
HRESET
SYSCLK
Mode Input Timing Diagram
period, to ensure that another master asserting TS on the following clock will not con-
before the first opportunity for another master to assert ARTRY. Output valid and
Figure 7-3 on page
IVKH
symbolizes the time input signals (I) reach the valid state (V) relative to
t MVRH
Figure 7-2 on page 23
24. The nominal precharge width for TS is 0.5 × t
VM
(signal)(state)(reference)(state)
KHOV
for sample timing.
SYSCLK
t MXRH
symbolizes the time from SYSCLK (K)
; that is, it should be high imped-
for inputs and
PC7457
SYSCLK
23
,