PCX7457VGH1000NC Atmel, PCX7457VGH1000NC Datasheet - Page 6

• Manufacturer Part Number: PCX7457VGH1000NC
• Description: IC MPU 32BIT 1000MHZ 483CBGA
• Manufacturer: Atmel

Specifications of PCX7457VGH1000NC

• Processor Type: PowerPC 32-Bit RISC
• Speed: 1.0GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 483-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

6
PC7457
• Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three
• Rename buffers
• Dispatch unit
• Completion unit
• Separate on-chip L1 Instruction and data caches (Harvard Architecture)
instructions, respectively, in a cycle. Instruction dispatch requires the following:
– Instructions can be dispatched only from the three lowest IQ entries – IQ0, IQ1, and
– A maximum of three instructions can be dispatched to the issue queues per clock
– Space must be available in the CQ for an instruction to dispatch (this includes
– 16 GPR rename buffers
– 16 FPR rename buffers
– 16 VR rename buffers
– Decode/dispatch stage fully decodes each instruction
– The completion unit retires an instruction from the 16-entry completion queue (CQ)
– Guarantees sequential programming model (precise exception model)
– Monitors all dispatched instructions and retires them in order
– Tracks unresolved branches and flushes instructions after a mispredicted branch
– Retires as many as three instructions per clock cycle
– 32 Kbyte, eight-way set-associative instruction and data caches
– Pseudo least-recently-used (PLRU) replacement algorithm
– 32-byte (eight-word) L1 cache block
– Physically indexed/physical tags
– Cache write-back or write-through operation programmable on a per-page or per-
Dedicated adder calculates effective addresses (EAs)
Supports store gathering
Performs alignment, normalization, and precision conversion for floating-point data
Executes cache control and TLB instructions
Performs alignment, zero padding, and sign extension for integer data
Supports hits under misses (multiple outstanding misses)
Supports both big- and little-endian modes, including misaligned little-endian
accesses
IQ2
cycle
instructions that are assigned a space in the CQ but not in an issue queue)
when all instructions ahead of it have been completed, the instruction has finished
execution, and no exceptions are pending
block basis
5345D–HIREL–07/06