MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 94

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Step 7: Enable TDM. The TDMs are enabled via the SI global mode register, SIGMR. For
more information on SIGMR programming, see page 7-77 of the MC68360 User’s Manual
and page 16-113 of the MPC860 User’s Manual. See Table 6-3 for SIGMR bit settings.
The following example enables both TDM channels for 32 entries.
Note that SIGMR[RDM] must be 0b1x if TDMb is used even if TDMa is not enabled.
Step 8. If shadow RAM is used, the SI command register (SICMR) is used to alternate
between normal and shadow RAM routings. For more information on SICMR
programming, see page 7-87 of the MC68360 user’s manual and page 16-122 of the
MPC860 user’s manual.
To enable both the Rx and Tx normal RAM area, use the following command:
To enable both the Rx and TX shadow RAM area, use the following command:
Change this entry dynamically to allow switching between the shadow and normal RAM.
Step 9. Initialize general SCCx mode reg high, GSMR_H (see Table 6-4). For more
information on GSMR programming, see page 7-111 of the MC68360 User’s Manual and
page 16-148 of the MPC860 User’s Manual.
ENB
ENA
RDM
IPR
GDE
TCRC
REVD
TRX
TTX
CDP
CTSP
Name
SIGMR = 0x0E;
SICMR = 0x00;
SICMR = 0xF0;
Name
No. of Bits
Freescale Semiconductor, Inc.
For More Information On This Product,
1
1
2
1
1
1
1
1
Number of Bits
Table 6-4. GSMR_H Bit Settings
Table 6-3. SIGMR Bit Settings
Infrared RX polarity, only on 860MH
Glitch detect enable
Transparent CRC
Reverse data
Transparent receiver
Transparent transmitter
CD pulse
CTS pulse
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/* enable TDMa, TDMb, each 32 entries, no shadow */
1
1
2
/* enable Rx and Tx shadow RAM on both TDMs */
/* enable Rx and Tx normal RAM */
QMC Supplement
Description
Enable TDMb
Enable TDMa
RAM division mode
Description
X
X
System-specific
0
0
0
1
1
System-specific
System-specific
System-specific
Setting
Setting