MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 103

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

/* GSMR_H1 is zero from reset */
/* GSMR_L1 is zero from reset */
inittsatr(4);
chbd = (struct descs *)((int)(pdpr->SCC1.MBASE));
pdpr->GSMR_L1.MODE = 0xA;
pdpr->GSMR_H1.CDP = 1;
pdpr->GSMR_H1.CTSP = 1;
pdpr->GSMR_H1.CDS = 1;
pdpr->GSMR_H1.CTSS = 1;
pdpr->SCC1.MCBASE = 0x1_0000; /* BD base located 0x1_0000 */
pdpr->SCC1.INTBASE = 0xF000;
pdpr->SCC1.MRBLR = 60;
pdpr->SCC1.GRFTHR = 1;
pdpr->SCC1.GRFCNT = 1;
pdpr->SCC1.C_MASK32 = 0xDEBB20E3;/* init 32-bit CRC const */
pdpr->SCC1.C_MASK16 = 0xF0B8; /* init 16-bit CRC const */
pdpr->SCC1.INTPTR = pdpr->SCC1.INTBASE;/* init intptr */
pdpr->SCC1.TSATR[3].W = 1;
pdpr->SCC1.Tx_S_PTR = (short *)(pdpr->SCC1.MCBASE+0x20);/* init pntr to
TSATTx table */
pdpr->SCC1.TxPTR = pdpr->SCC1.Tx_S_PTR;/* init curr TSATTx pntr */
pdpr->SCC1.Rx_S_PTR = (short *)(pdpr->SCC1.MCBASE+0x20);/* init pntr to
TSATRx table */
pdpr->SCC1.RxPTR = pdpr->SCC1.Rx_S_PTR;/* init curr TSATRx pntr */
pdpr->SCC1.QMC_STATE = 0x8000;/* init QMC-STATE */
pdpr->ch[0].RBASE = 0;
pdpr->ch[0].TBASE = 8;
pdpr->ch[1].RBASE = 0x10;
pdpr->ch[1].TBASE = 0x18;
pdpr->ch[2].RBASE = 0x20;
pdpr->ch[2].TBASE = 0x28;
pdpr->ch[3].RBASE = 0x30;
pdpr->ch[3].TBASE = 0x38;
for (v1 = 0; v1 < 4; v1++)
{
pdpr->ch[v1].ZISTATE = 0x100;
pdpr->ch[v1].RSTATE = 0x3900_0000;
pdpr->ch[v1].TSTATE = 0x3800_0000;
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Chapter 6. QMC Initialization
/* enable CD* pulse */
/* enable CTS* pulse */
/* enable CDS* sampling */
/* enable CTS* sampling */
/* select QMC mode */
/* interrupt table base 0xF000 */
/* set receive buffer length to 60 */
/* 1 receive frame to intrpt */
/* 1 receive frame to intrpt */
/* last time slot */
/* locate CH0 RxBDS at 0 */
/* locate CH0 TxBDS at 8 */
/* locate CH1 RxBDS 0x10 */
/* locate CH1 TxBDS 0x18 */
/* locate CH2 RxBDS 0x20 */
/* locate CH2 TxBDS 0x28 */
/* locate CH3 RxBDS 0x30 */
/* locate CH3 TXBDS 0x38 */