MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 137

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Appendix C
Connecting ISDN Multiple
S/T or U Interfaces to QUICC32
C0
C0
Using IDL or GCI protocols, the MC145574 (S/T interface) and the MC145572
(U interface) can be gluelessly interfaced to members of the MC68302 family for low-cost,
active-ISDN basic rate terminal applications.
For applications needing to support more than one basic rate interface (BRI), such as LAN/
WAN bridges, PBX, line cards or multiple-line terminal adaptors, a system solution using
multiple MC145574s or MC145572s can be built around a QUICC32 (MC68MH360).
The QUICC32 and the QMC (QUICC’s multichannel controller) protocol are useful for
such ISDN applications requiring several logical channels on one physical medium.
This appendix shows how multiple MC145574s or MC145572s can be connected to a
QUICC32, describing the level-1 connections and explaining the data flow through the
devices.
No software issues are addressed in this appendix.
C.1 The QMC Protocol
Based upon the IDL bus, the QMC protocol implemented on the QUICC32 generates a
TDM (time-division multiplexing) bus with programmable time slots for each ISDN
interface. With 32 time slots, each carrying 8 consecutive bits forming 64-Kbps channels,
a 2-Mbps TDM line (roughly equivalent to a CEPT/E1 link) can be created.
Time slot zero (TS0) is dedicated to the first B1 channel, with TS1 assigned to the first B2
channel and TS2 to the first D channel. Even though only 2 bits are used for signaling, the
D channel has 8 bits reserved on the TDM link since the QMC microcode must process data
on 8-bit boundaries for correct delineation of channels. The unused 6 bits are masked in the
QMC time slot assignment table.
Since the TDM line allows a maximum of 32 channels, the above process of routing
channels to time slots (that is, the second B1 channel routed to TS3 and so on) can be
repeated for up to 10 BRIs.
Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
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