MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 54

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RESET:
Reset:
2.4.2.3 INTMSK—Interrupt Mask (Transparent Mode)
Each event defined in the interrupt circular queue entry maps directly to a bit in INTMSK
as shown in Figure 2-13. There is one mask bit for each event—UN (bit 11), BSY (bit 13),
TXB (bit 14) and RXB (bit 15). Bits that do not map to an event are reserved. Reserved bits
must be set to zero.
This register is initialized by the host before operation.
INTERRUPT TABLE ENTRY:
INTMSK:
2.4.2.4 TRNSYNC—Transparent Synchronization
In transparent mode, the TRNSYNC register controls the synchronization for single time
slots or superchannel applications.
When sending a transparent message over several time slots, it is necessary to know in
which time slot the first byte of data appears.
The TRNSYNC word-length register is divided into two parts with the high byte
controlling the first received time slot and the low byte controlling the transmitter
synchronization.
RESERVED
0
V
0
0
0
• 0 = No interrupt request is generated and no new entry is written in the circular
• 1 = Interrupts are enabled.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
interrupt table.
W
1
0
1
0
Figure 2-13. INTMSK and Interrupt Table Entry (Transparent Mode)
RES
RESERVED
2
0
2
0
This register has no meaning if the SYNC bit in the channel
mode register (CHAMR) is cleared (0).
RES
Freescale Semiconductor, Inc.
3
0
3
0
For More Information On This Product,
4
–
0
4
0
5
0
5
0
Go to: www.freescale.com
RESERVED
6
0
6
0
CHANNEL NUMBER
QMC Supplement
7
0
7
0
Note
8
0
8
0
9
0
9
0
RES
RES
10
10
0
0
UN
11
11
0
0
RES
INTERRUPT MASK BITS
12
12
0
0
BSY
13
13
0
0
TXB
14
14
0
0
RXB
15
15
0
0