MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 116

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

In the worst-case scenario, all channels open and close a buffer during the same TDM frame
resulting in the peak load all performance calculations are based on. This peak load is far
from the norm and can be controlled by the transmitter spreading the starting point of
transmit buffers over several TDM frames.
In multimaster systems, bus latency may affect the performance of the device. The
maximum external bus latency figures shown in Table 8-4 are measured from the assertion
of the BR (bus request) to the assertion of the BGACK (bus grant acknowledge); that is,
from start of bus request output being active until the cycle is completed. For multimaster
systems, bus arbitration overhead is included. Latencies of up to 40 clocks were simulated;
for values over 40, the acceptable latency may be larger.
Table 8-4 shows average maximum acceptable bus latencies, meaning the device can
tolerate longer bus delays if they are infrequent. For lengthy delays, a larger FIFO can pick
up the slack, continuing emptying or filling depending on the data flow direction.
Therefore, the larger the FIFO the more tolerant the system is to infrequent peaks in bus
delays. However, the average acceptable bus latency still depends on the overall data rate
and frame length and not on the FIFO size.
Not supported
Not supported
9 clocks
8 clocks
40 clocks
33 clocks
8 clocks
Not supported
40 clocks
Maximum Acceptable Latency
25 MHz
(Bus Cycles)
Freescale Semiconductor, Inc.
For More Information On This Product,
12
11
>40
35
>40
>40
24
23
>40
33 MHZ
Table 8-4. Simulated Latencies
Go to: www.freescale.com
SCC1: Ethernet; SCC2: 16 x 64 Kbps; SCC3: 16 x 64 Kbps
SCC1: Ethernet; SCC2: 16 x 64 Kbps; SCC3: 16 x 64 Kbps;
SCC4: 64 Kbps HDLC
SCC1: 32 x 64 Kbps. Serial bit rate 2.048 Mbps (E1/CEPT)
SCC1: 32 x 64 Kbps; SCC2: 64 Kbps; SCC3: 64 Kbps; SCC4: 64 Kbps;
all HDLC
QMC with 24 channels. Serial bit rate 1.544 Mbps (T1)
SCC1: 24 x 64 Kbps; SCC2: 64 Kbps; SCC3: 64 Kbps; SCC4: 64 Kbps;
all HDLC
SCC1: Ethernet; SCC2: 12 x 64 Kbps; SCC3: 12 x 64 Kbps.
TDM bit rate = 1.544 Mbps
SCC1: Ethernet; SCC2: 12 x 64 Kbps; SCC3: 12 x 64 Kbps;
SCC4: 64-Kbps HDLC.
TDM bit rate = 1.544 Mbps
SCC1: 16 x 128 Kbps. TDM bit rate = 2.048 Mbps
QMC Supplement
Channel Combinations