MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 115

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.3 Bus Latency and Peak Load
Each time slot is 8 bits, but the QMC protocol transfers 32 bits of data whenever possible.
Thus, for each active channel operating within large frames, two 32-bit SDMA data
transfers (one for Tx and one for Rx) occur approximately every fourth TDM frame (every
500 s in CEPT/T1 interfaces). During buffer closing or opening, load will increase
approximately 3 to 4 times. Table 8-3 illustrates the bus activities involved when one QMC
channel switches from one Tx HDLC frame to the next.
In Table 8-3, the frame number refers to the 125- s frame; the numbering is arbitrary but
sequential. The actions refer to the visible functions executed on the CPM. The number of
external bus cycles executed by the CPM represents the load on the bus.
The sequence in Table 8-3 starts when the last 32 bits are read from a buffer. One byte is
transferred over the TDM link per frame over the next four 125- s frames. Then the CRC
is sent. In this case, it is a 16-bit CRC requiring two time slots over the next two frames.
The heavy load on the bus starts when the CPM must close the buffer in frame 8. At this
point the CPM needs three accesses to the bus to read and write to the interrupt table and
update the buffer descriptor’s status. In the following frame, the next buffer is opened
requiring three accesses to read the status and length, read the data pointer and read the data.
Note: The table assumes the channel uses one time slot per TDM frame and that no PAD characters,
preceding flags or flag sharing is used.
Freescale Semiconductor, Inc.
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For More Information On This Product,
Table 8-3. QMC Actions in Tx Buffer Switch
Number
Frame
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Read long word from buffer
(last in frame)
Send byte
Send byte
Send byte
Send last byte in frame
Send CRC
Send CRC
Send flag
Read interrupt table
Write interrupt table
Write BD
Send flag
Read next BD status/length
Read BD data pointer
Read data
Send first byte of next frame
Chapter 8. Performance
Actions
Bus Cycles
Number of
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0
0
0
0
0
0
3
3
0