MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 117

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MC68MH360AI33L

Manufacturer Part Number
MC68MH360AI33L
Description
IC MPU QUICC 33MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360AI33L

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68MH360AI33L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 9
Multi-Subchannel (MSC) Microcode
90
90
The RISC processor in the PowerQUICC has an option to execute microcode from the
internal dual-ported RAM. Motorola uses this feature to enhance existing protocols or
implement additional protocols. Customers can purchase RAM microcodes in an object-
code format and download it to the PowerQUICC dual-ported RAM during system
initialization.
The RAM microcode is provided by Motorola as a set of S records that can be downloaded
directly to an application development system or stored in a system EPROM; for more
information on S records, see Appendix C of the M68000 Family Programmer’s Reference
Manual. After system reset, the binary of the microcode should be copied to the dual-ported
RAM. The QUICC registers, including the RISC controller configuration register (RCCR),
should be initialized as specified in the microcode RAM documentation. Before the RISC
is used in the system, the user should issue a reset command to the communications
processor command register (CR). The microcode RAM functions are available in addition
to all protocols available in the standard QUICC microcode ROM.
9.1 MSC Microcode Features
The multi-subchannel (MSC) microcode is a downloadable microcode for the MPC860MH
and has the following key features:
• General
• Performance
— Multiple subchannels within a single 8-bit time slot
— Bit resolution for subchannels
— Up to 32 independent communications channels for both Rx and Tx
— Supports either transparent or HDLC protocols per subchannel
— 32 channels + 10-Mbps ethernet support at 40-MHz system clock
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 9. Multi-Subchannel (MSC) Microcode
Go to: www.freescale.com

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