MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 51

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Reset:
2.4.2.1 CHAMR—Channel Mode Register (Transparent Mode)
The channel mode register is a word-length, host-initialized register. Figure 2-11 shows the
channel mode register for transparent mode.
Table 2-11 describes the channel mode register’s fields for transparent operation. Boldfaced
parameters must be initialized by the user.
MODE
22
24
28
2C
2E
30
34
38
3C
3E
Offset
0
0
Notes: 1. All bits defined as reserved are cleared (0).
RD
1
0
TMRBLR
RSTATE
RBPTR
RPACK
ZDSTATE
RES
TRNSYNC
RES
Figure 2-11. CHAMR—Channel Mode Register (Transparent Mode)
Table 2-10. Channel-Specific Transparent Parameters (Continued)
2. For the 68360, the bit numbering is reversed. See Appendix A for more information.
Name
2
0
1
ENT
Freescale Semiconductor, Inc.
3
0
Width
16
32
32
16
16
32
32
32
16
16
For More Information On This Product,
RES’D
4
0
Transparent maximum receive buffer length (host-initialized entry)—Defines the
maximum number of bytes written to a receive buffer before moving to the next
buffer for this channel. Note that this value must be a multiple of 4 bytes as the
QMC works on long-word alignment.
Rx internal state —Initialize to 0x3900
initialize to 0x3100
“RSTATE—Rx Internal State (Transparent Mode),” for more information.
Rx internal data pointer—Points to current address of specific channel.
Rx buffer descriptor pointer (host-initialized to RBASE, prior to operation or due to
a fatal error)—Contains the offset from MCBASE to the current receive buffer. See
Figure 2-2. MCBASE + RBPTR gives the address for the BD in use.
Rx internal byte count—Per Channel: Number of remaining bytes in buffer
(Rx temp)—Packs 4 bytes to 1 long word before writing to buffer.
Zero deletion machine state—(Host-initialized to 0x0000
0x1800
(global overrun, busy) before channel initialization.)—Contains the previous state
of the zero-deletion state machine. The middle 2 bytes, represented by zeros in the
initialization value above, holds the received pattern during reception. A window of
16 bits shows the history of what is received on this logical channel.
Transparent synchronization—In transparent mode, this register controls
synchronization for single time slots or superchannel applications. See
Section 2.4.2.4, “TRNSYNC—Transparent Synchronization.”
Chapter 2. QMC Memory Organization
SYNC
5
0
Go to: www.freescale.com
_
0080 in transparent mode, prior to operation and after a fatal Rx error
RES
6
0
_
POL
0000 AT = 1, Motorola mode for 860MH. See Section 2.4.2.5,
7
0
8
0
0
Description
9
0
0
_
0000 FC = 9, Motorola mode for MH360,
10
0
RESERVED
11
0
_
12
0080 in HDLC mode,
0
13
0
0
14
0
15
0